[PATCH] D91724: [HardwareLoops] Change order of SCEV expression construction for InitLoopCount.

Thu Sep 2 19:56:28 PDT 2021

shchenz added a comment.

In D91724#2981131 <https://reviews.llvm.org/D91724#2981131>, @reames wrote:

> Glanced at this due to being CCed on pr51714.
>
> This patch does not look correct on first glance.  If backedge taken count is UINT_MAX for the narrower type, doing the increment in the narrow type produces zext(0) e.g. zero, whereas doing the zext(BTC)+1 does not.  Unless there's something in the code which prevents BTC=UINT_MAX/TC=0, I suspect that's the cause of the miscompile being observed in that bug and this patch should be reverted.

Thanks @reames 
reverted in 34badc409cc452575c538c4b6449546adc38f121 <https://reviews.llvm.org/rG34badc409cc452575c538c4b6449546adc38f121>

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  https://reviews.llvm.org/D91724/new/

https://reviews.llvm.org/D91724