[llvm] 498e8ae - [RISCV] Add Zba command line to rv64i-exhaustive-w-insts.ll
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 2 08:36:45 PDT 2021
Author: Craig Topper
Date: 2021-09-02T08:36:27-07:00
New Revision: 498e8ae412a17dc8d9b8dd47ba3fca068f10b4d3
URL: https://github.com/llvm/llvm-project/commit/498e8ae412a17dc8d9b8dd47ba3fca068f10b4d3
DIFF: https://github.com/llvm/llvm-project/commit/498e8ae412a17dc8d9b8dd47ba3fca068f10b4d3.diff
LOG: [RISCV] Add Zba command line to rv64i-exhaustive-w-insts.ll
Zba adds a zext.w pseudoinstruction using ADDUW. This can simplify
the generated code for many of these tests.
There are at least 2 suboptimal cases in this config that I've marked
with TODOs.
Added:
Modified:
llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll b/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
index 66f06cde47eb..c4b15760d682 100644
--- a/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
+++ b/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV64I
+; RUN: | FileCheck %s -check-prefixes=RV64,RV64I
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+experimental-zba < %s \
+; RUN: | FileCheck %s -check-prefixes=RV64,RV64ZBA
; The patterns for the 'W' suffixed RV64I instructions have the potential of
; missing cases. This file checks all the variants of
@@ -9,82 +11,82 @@
; The 64-bit add instruction can safely be used when the result is anyext.
define i32 @aext_addw_aext_aext(i32 %a, i32 %b) nounwind {
-; RV64I-LABEL: aext_addw_aext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_addw_aext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a1
+; RV64-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
define i32 @aext_addw_aext_sext(i32 %a, i32 signext %b) nounwind {
-; RV64I-LABEL: aext_addw_aext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_addw_aext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a1
+; RV64-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
define i32 @aext_addw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: aext_addw_aext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_addw_aext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a1
+; RV64-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
define i32 @aext_addw_sext_aext(i32 signext %a, i32 %b) nounwind {
-; RV64I-LABEL: aext_addw_sext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_addw_sext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a1
+; RV64-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
define i32 @aext_addw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: aext_addw_sext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_addw_sext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a1
+; RV64-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
define i32 @aext_addw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: aext_addw_sext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_addw_sext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a1
+; RV64-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
define i32 @aext_addw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
-; RV64I-LABEL: aext_addw_zext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_addw_zext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a1
+; RV64-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
define i32 @aext_addw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: aext_addw_zext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_addw_zext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a1
+; RV64-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
define i32 @aext_addw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: aext_addw_zext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_addw_zext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a1
+; RV64-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
@@ -92,82 +94,82 @@ define i32 @aext_addw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
; Always select addw when a signext result is required.
define signext i32 @sext_addw_aext_aext(i32 %a, i32 %b) nounwind {
-; RV64I-LABEL: sext_addw_aext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_addw_aext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a1
+; RV64-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
define signext i32 @sext_addw_aext_sext(i32 %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sext_addw_aext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_addw_aext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a1
+; RV64-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
define signext i32 @sext_addw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: sext_addw_aext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_addw_aext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a1
+; RV64-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
define signext i32 @sext_addw_sext_aext(i32 signext %a, i32 %b) nounwind {
-; RV64I-LABEL: sext_addw_sext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_addw_sext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a1
+; RV64-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
define signext i32 @sext_addw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sext_addw_sext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_addw_sext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a1
+; RV64-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
define signext i32 @sext_addw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: sext_addw_sext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_addw_sext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a1
+; RV64-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
define signext i32 @sext_addw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
-; RV64I-LABEL: sext_addw_zext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_addw_zext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a1
+; RV64-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
define signext i32 @sext_addw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sext_addw_zext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_addw_zext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a1
+; RV64-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
define signext i32 @sext_addw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: sext_addw_zext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_addw_zext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a1
+; RV64-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
@@ -182,6 +184,12 @@ define zeroext i32 @zext_addw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_addw_aext_aext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: addw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
@@ -193,6 +201,12 @@ define zeroext i32 @zext_addw_aext_sext(i32 %a, i32 signext %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_addw_aext_sext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: addw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
@@ -204,6 +218,12 @@ define zeroext i32 @zext_addw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_addw_aext_zext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: addw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
@@ -215,6 +235,12 @@ define zeroext i32 @zext_addw_sext_aext(i32 signext %a, i32 %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_addw_sext_aext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: addw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
@@ -226,6 +252,12 @@ define zeroext i32 @zext_addw_sext_sext(i32 signext %a, i32 signext %b) nounwind
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_addw_sext_sext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: addw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
@@ -237,6 +269,12 @@ define zeroext i32 @zext_addw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_addw_sext_zext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: addw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
@@ -248,6 +286,12 @@ define zeroext i32 @zext_addw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_addw_zext_aext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: addw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
@@ -259,6 +303,12 @@ define zeroext i32 @zext_addw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_addw_zext_sext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: addw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
@@ -270,6 +320,12 @@ define zeroext i32 @zext_addw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_addw_zext_zext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: addw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
@@ -277,82 +333,82 @@ define zeroext i32 @zext_addw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind
; 64-bit sub is safe for an anyext result.
define i32 @aext_subw_aext_aext(i32 %a, i32 %b) nounwind {
-; RV64I-LABEL: aext_subw_aext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: subw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_subw_aext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: subw a0, a0, a1
+; RV64-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
define i32 @aext_subw_aext_sext(i32 %a, i32 signext %b) nounwind {
-; RV64I-LABEL: aext_subw_aext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: subw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_subw_aext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: subw a0, a0, a1
+; RV64-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
define i32 @aext_subw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: aext_subw_aext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: subw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_subw_aext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: subw a0, a0, a1
+; RV64-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
define i32 @aext_subw_sext_aext(i32 signext %a, i32 %b) nounwind {
-; RV64I-LABEL: aext_subw_sext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: subw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_subw_sext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: subw a0, a0, a1
+; RV64-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
define i32 @aext_subw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: aext_subw_sext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: subw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_subw_sext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: subw a0, a0, a1
+; RV64-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
define i32 @aext_subw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: aext_subw_sext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: subw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_subw_sext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: subw a0, a0, a1
+; RV64-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
define i32 @aext_subw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
-; RV64I-LABEL: aext_subw_zext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: subw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_subw_zext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: subw a0, a0, a1
+; RV64-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
define i32 @aext_subw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: aext_subw_zext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: subw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_subw_zext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: subw a0, a0, a1
+; RV64-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
define i32 @aext_subw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: aext_subw_zext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: subw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_subw_zext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: subw a0, a0, a1
+; RV64-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
@@ -360,82 +416,82 @@ define i32 @aext_subw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
; Always select subw for a signext result.
define signext i32 @sext_subw_aext_aext(i32 %a, i32 %b) nounwind {
-; RV64I-LABEL: sext_subw_aext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: subw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_subw_aext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: subw a0, a0, a1
+; RV64-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
define signext i32 @sext_subw_aext_sext(i32 %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sext_subw_aext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: subw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_subw_aext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: subw a0, a0, a1
+; RV64-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
define signext i32 @sext_subw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: sext_subw_aext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: subw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_subw_aext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: subw a0, a0, a1
+; RV64-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
define signext i32 @sext_subw_sext_aext(i32 signext %a, i32 %b) nounwind {
-; RV64I-LABEL: sext_subw_sext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: subw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_subw_sext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: subw a0, a0, a1
+; RV64-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
define signext i32 @sext_subw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sext_subw_sext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: subw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_subw_sext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: subw a0, a0, a1
+; RV64-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
define signext i32 @sext_subw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: sext_subw_sext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: subw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_subw_sext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: subw a0, a0, a1
+; RV64-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
define signext i32 @sext_subw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
-; RV64I-LABEL: sext_subw_zext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: subw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_subw_zext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: subw a0, a0, a1
+; RV64-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
define signext i32 @sext_subw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sext_subw_zext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: subw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_subw_zext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: subw a0, a0, a1
+; RV64-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
define signext i32 @sext_subw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: sext_subw_zext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: subw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_subw_zext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: subw a0, a0, a1
+; RV64-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
@@ -449,6 +505,12 @@ define zeroext i32 @zext_subw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_subw_aext_aext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: subw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
@@ -460,6 +522,12 @@ define zeroext i32 @zext_subw_aext_sext(i32 %a, i32 signext %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_subw_aext_sext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: subw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
@@ -471,6 +539,12 @@ define zeroext i32 @zext_subw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_subw_aext_zext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: subw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
@@ -482,6 +556,12 @@ define zeroext i32 @zext_subw_sext_aext(i32 signext %a, i32 %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_subw_sext_aext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: subw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
@@ -493,6 +573,12 @@ define zeroext i32 @zext_subw_sext_sext(i32 signext %a, i32 signext %b) nounwind
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_subw_sext_sext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: subw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
@@ -504,6 +590,12 @@ define zeroext i32 @zext_subw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_subw_sext_zext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: subw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
@@ -515,6 +607,12 @@ define zeroext i32 @zext_subw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_subw_zext_aext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: subw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
@@ -526,6 +624,12 @@ define zeroext i32 @zext_subw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_subw_zext_sext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: subw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
@@ -537,6 +641,12 @@ define zeroext i32 @zext_subw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_subw_zext_zext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: subw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
@@ -544,163 +654,163 @@ define zeroext i32 @zext_subw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind
; 64-bit sll is a safe choice for an anyext result.
define i32 @aext_sllw_aext_aext(i32 %a, i32 %b) nounwind {
-; RV64I-LABEL: aext_sllw_aext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sllw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_sllw_aext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: sllw a0, a0, a1
+; RV64-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
define i32 @aext_sllw_aext_sext(i32 %a, i32 signext %b) nounwind {
-; RV64I-LABEL: aext_sllw_aext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sllw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_sllw_aext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: sllw a0, a0, a1
+; RV64-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
define i32 @aext_sllw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: aext_sllw_aext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sllw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_sllw_aext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: sllw a0, a0, a1
+; RV64-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
define i32 @aext_sllw_sext_aext(i32 signext %a, i32 %b) nounwind {
-; RV64I-LABEL: aext_sllw_sext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sllw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_sllw_sext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: sllw a0, a0, a1
+; RV64-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
define i32 @aext_sllw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: aext_sllw_sext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sllw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_sllw_sext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: sllw a0, a0, a1
+; RV64-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
define i32 @aext_sllw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: aext_sllw_sext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sllw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_sllw_sext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: sllw a0, a0, a1
+; RV64-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
define i32 @aext_sllw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
-; RV64I-LABEL: aext_sllw_zext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sllw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_sllw_zext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: sllw a0, a0, a1
+; RV64-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
define i32 @aext_sllw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: aext_sllw_zext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sllw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_sllw_zext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: sllw a0, a0, a1
+; RV64-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
define i32 @aext_sllw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: aext_sllw_zext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sllw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_sllw_zext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: sllw a0, a0, a1
+; RV64-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
define signext i32 @sext_sllw_aext_aext(i32 %a, i32 %b) nounwind {
-; RV64I-LABEL: sext_sllw_aext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sllw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_sllw_aext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: sllw a0, a0, a1
+; RV64-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
define signext i32 @sext_sllw_aext_sext(i32 %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sext_sllw_aext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sllw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_sllw_aext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: sllw a0, a0, a1
+; RV64-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
define signext i32 @sext_sllw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: sext_sllw_aext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sllw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_sllw_aext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: sllw a0, a0, a1
+; RV64-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
define signext i32 @sext_sllw_sext_aext(i32 signext %a, i32 %b) nounwind {
-; RV64I-LABEL: sext_sllw_sext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sllw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_sllw_sext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: sllw a0, a0, a1
+; RV64-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
define signext i32 @sext_sllw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sext_sllw_sext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sllw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_sllw_sext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: sllw a0, a0, a1
+; RV64-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
define signext i32 @sext_sllw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: sext_sllw_sext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sllw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_sllw_sext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: sllw a0, a0, a1
+; RV64-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
define signext i32 @sext_sllw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
-; RV64I-LABEL: sext_sllw_zext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sllw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_sllw_zext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: sllw a0, a0, a1
+; RV64-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
define signext i32 @sext_sllw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sext_sllw_zext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sllw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_sllw_zext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: sllw a0, a0, a1
+; RV64-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
define signext i32 @sext_sllw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: sext_sllw_zext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sllw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_sllw_zext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: sllw a0, a0, a1
+; RV64-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
@@ -714,6 +824,12 @@ define zeroext i32 @zext_sllw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sllw_aext_aext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sllw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
@@ -725,6 +841,12 @@ define zeroext i32 @zext_sllw_aext_sext(i32 %a, i32 signext %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sllw_aext_sext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sllw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
@@ -736,6 +858,12 @@ define zeroext i32 @zext_sllw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sllw_aext_zext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sllw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
@@ -747,6 +875,12 @@ define zeroext i32 @zext_sllw_sext_aext(i32 signext %a, i32 %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sllw_sext_aext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sllw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
@@ -758,6 +892,12 @@ define zeroext i32 @zext_sllw_sext_sext(i32 signext %a, i32 signext %b) nounwind
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sllw_sext_sext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sllw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
@@ -769,6 +909,12 @@ define zeroext i32 @zext_sllw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sllw_sext_zext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sllw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
@@ -780,6 +926,12 @@ define zeroext i32 @zext_sllw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sllw_zext_aext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sllw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
@@ -791,6 +943,12 @@ define zeroext i32 @zext_sllw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sllw_zext_sext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sllw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
@@ -802,168 +960,174 @@ define zeroext i32 @zext_sllw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sllw_zext_zext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sllw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
define i32 @aext_srlw_aext_aext(i32 %a, i32 %b) nounwind {
-; RV64I-LABEL: aext_srlw_aext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srlw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_srlw_aext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: srlw a0, a0, a1
+; RV64-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
define i32 @aext_srlw_aext_sext(i32 %a, i32 signext %b) nounwind {
-; RV64I-LABEL: aext_srlw_aext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srlw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_srlw_aext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: srlw a0, a0, a1
+; RV64-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
define i32 @aext_srlw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: aext_srlw_aext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srlw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_srlw_aext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: srlw a0, a0, a1
+; RV64-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
define i32 @aext_srlw_sext_aext(i32 signext %a, i32 %b) nounwind {
-; RV64I-LABEL: aext_srlw_sext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srlw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_srlw_sext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: srlw a0, a0, a1
+; RV64-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
define i32 @aext_srlw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: aext_srlw_sext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srlw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_srlw_sext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: srlw a0, a0, a1
+; RV64-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
define i32 @aext_srlw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: aext_srlw_sext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srlw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_srlw_sext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: srlw a0, a0, a1
+; RV64-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
define i32 @aext_srlw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
-; RV64I-LABEL: aext_srlw_zext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srlw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_srlw_zext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: srlw a0, a0, a1
+; RV64-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
define i32 @aext_srlw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: aext_srlw_zext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srlw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_srlw_zext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: srlw a0, a0, a1
+; RV64-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
define i32 @aext_srlw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: aext_srlw_zext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srlw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_srlw_zext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: srlw a0, a0, a1
+; RV64-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
define signext i32 @sext_srlw_aext_aext(i32 %a, i32 %b) nounwind {
-; RV64I-LABEL: sext_srlw_aext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srlw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_srlw_aext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: srlw a0, a0, a1
+; RV64-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
define signext i32 @sext_srlw_aext_sext(i32 %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sext_srlw_aext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srlw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_srlw_aext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: srlw a0, a0, a1
+; RV64-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
define signext i32 @sext_srlw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: sext_srlw_aext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srlw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_srlw_aext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: srlw a0, a0, a1
+; RV64-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
define signext i32 @sext_srlw_sext_aext(i32 signext %a, i32 %b) nounwind {
-; RV64I-LABEL: sext_srlw_sext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srlw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_srlw_sext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: srlw a0, a0, a1
+; RV64-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
define signext i32 @sext_srlw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sext_srlw_sext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srlw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_srlw_sext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: srlw a0, a0, a1
+; RV64-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
define signext i32 @sext_srlw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: sext_srlw_sext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srlw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_srlw_sext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: srlw a0, a0, a1
+; RV64-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
define signext i32 @sext_srlw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
-; RV64I-LABEL: sext_srlw_zext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srlw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_srlw_zext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: srlw a0, a0, a1
+; RV64-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
define signext i32 @sext_srlw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sext_srlw_zext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srlw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_srlw_zext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: srlw a0, a0, a1
+; RV64-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
define signext i32 @sext_srlw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: sext_srlw_zext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srlw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_srlw_zext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: srlw a0, a0, a1
+; RV64-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
@@ -975,6 +1139,12 @@ define zeroext i32 @zext_srlw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_srlw_aext_aext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: srlw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
@@ -986,6 +1156,12 @@ define zeroext i32 @zext_srlw_aext_sext(i32 %a, i32 signext %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_srlw_aext_sext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: srlw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
@@ -997,6 +1173,12 @@ define zeroext i32 @zext_srlw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_srlw_aext_zext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: srlw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
@@ -1008,6 +1190,12 @@ define zeroext i32 @zext_srlw_sext_aext(i32 signext %a, i32 %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_srlw_sext_aext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: srlw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
@@ -1019,6 +1207,12 @@ define zeroext i32 @zext_srlw_sext_sext(i32 signext %a, i32 signext %b) nounwind
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_srlw_sext_sext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: srlw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
@@ -1030,6 +1224,12 @@ define zeroext i32 @zext_srlw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_srlw_sext_zext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: srlw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
@@ -1041,6 +1241,12 @@ define zeroext i32 @zext_srlw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_srlw_zext_aext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: srlw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
@@ -1052,6 +1258,12 @@ define zeroext i32 @zext_srlw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_srlw_zext_sext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: srlw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
@@ -1063,168 +1275,174 @@ define zeroext i32 @zext_srlw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_srlw_zext_zext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: srlw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
define i32 @aext_sraw_aext_aext(i32 %a, i32 %b) nounwind {
-; RV64I-LABEL: aext_sraw_aext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_sraw_aext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraw a0, a0, a1
+; RV64-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
define i32 @aext_sraw_aext_sext(i32 %a, i32 signext %b) nounwind {
-; RV64I-LABEL: aext_sraw_aext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_sraw_aext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraw a0, a0, a1
+; RV64-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
define i32 @aext_sraw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: aext_sraw_aext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_sraw_aext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraw a0, a0, a1
+; RV64-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
define i32 @aext_sraw_sext_aext(i32 signext %a, i32 %b) nounwind {
-; RV64I-LABEL: aext_sraw_sext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_sraw_sext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraw a0, a0, a1
+; RV64-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
define i32 @aext_sraw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: aext_sraw_sext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_sraw_sext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraw a0, a0, a1
+; RV64-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
define i32 @aext_sraw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: aext_sraw_sext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_sraw_sext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraw a0, a0, a1
+; RV64-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
define i32 @aext_sraw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
-; RV64I-LABEL: aext_sraw_zext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_sraw_zext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraw a0, a0, a1
+; RV64-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
define i32 @aext_sraw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: aext_sraw_zext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_sraw_zext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraw a0, a0, a1
+; RV64-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
define i32 @aext_sraw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: aext_sraw_zext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_sraw_zext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraw a0, a0, a1
+; RV64-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
define signext i32 @sext_sraw_aext_aext(i32 %a, i32 %b) nounwind {
-; RV64I-LABEL: sext_sraw_aext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_sraw_aext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraw a0, a0, a1
+; RV64-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
define signext i32 @sext_sraw_aext_sext(i32 %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sext_sraw_aext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_sraw_aext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraw a0, a0, a1
+; RV64-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
define signext i32 @sext_sraw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: sext_sraw_aext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_sraw_aext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraw a0, a0, a1
+; RV64-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
define signext i32 @sext_sraw_sext_aext(i32 signext %a, i32 %b) nounwind {
-; RV64I-LABEL: sext_sraw_sext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_sraw_sext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraw a0, a0, a1
+; RV64-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
define signext i32 @sext_sraw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sext_sraw_sext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_sraw_sext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraw a0, a0, a1
+; RV64-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
define signext i32 @sext_sraw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: sext_sraw_sext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_sraw_sext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraw a0, a0, a1
+; RV64-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
define signext i32 @sext_sraw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
-; RV64I-LABEL: sext_sraw_zext_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_sraw_zext_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraw a0, a0, a1
+; RV64-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
define signext i32 @sext_sraw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sext_sraw_zext_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_sraw_zext_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraw a0, a0, a1
+; RV64-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
define signext i32 @sext_sraw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
-; RV64I-LABEL: sext_sraw_zext_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraw a0, a0, a1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_sraw_zext_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraw a0, a0, a1
+; RV64-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
@@ -1236,6 +1454,12 @@ define zeroext i32 @zext_sraw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sraw_aext_aext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sraw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
@@ -1247,6 +1471,12 @@ define zeroext i32 @zext_sraw_aext_sext(i32 %a, i32 signext %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sraw_aext_sext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sraw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
@@ -1258,6 +1488,12 @@ define zeroext i32 @zext_sraw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sraw_aext_zext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sraw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
@@ -1269,6 +1505,12 @@ define zeroext i32 @zext_sraw_sext_aext(i32 signext %a, i32 %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sraw_sext_aext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sraw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
@@ -1280,6 +1522,12 @@ define zeroext i32 @zext_sraw_sext_sext(i32 signext %a, i32 signext %b) nounwind
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sraw_sext_sext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sraw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
@@ -1291,6 +1539,12 @@ define zeroext i32 @zext_sraw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sraw_sext_zext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sraw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
@@ -1302,6 +1556,12 @@ define zeroext i32 @zext_sraw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sraw_zext_aext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sraw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
@@ -1313,6 +1573,12 @@ define zeroext i32 @zext_sraw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sraw_zext_sext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sraw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
@@ -1324,6 +1590,12 @@ define zeroext i32 @zext_sraw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sraw_zext_zext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sraw a0, a0, a1
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
@@ -1331,55 +1603,55 @@ define zeroext i32 @zext_sraw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind
; addiw should be selected when there is a signext result.
define i32 @aext_addiw_aext(i32 %a) nounwind {
-; RV64I-LABEL: aext_addiw_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addiw a0, a0, 1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_addiw_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: addiw a0, a0, 1
+; RV64-NEXT: ret
%1 = add i32 %a, 1
ret i32 %1
}
define i32 @aext_addiw_sext(i32 signext %a) nounwind {
-; RV64I-LABEL: aext_addiw_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addiw a0, a0, 2
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_addiw_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: addiw a0, a0, 2
+; RV64-NEXT: ret
%1 = add i32 %a, 2
ret i32 %1
}
define i32 @aext_addiw_zext(i32 zeroext %a) nounwind {
-; RV64I-LABEL: aext_addiw_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addiw a0, a0, 3
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_addiw_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: addiw a0, a0, 3
+; RV64-NEXT: ret
%1 = add i32 %a, 3
ret i32 %1
}
define signext i32 @sext_addiw_aext(i32 %a) nounwind {
-; RV64I-LABEL: sext_addiw_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addiw a0, a0, 4
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_addiw_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: addiw a0, a0, 4
+; RV64-NEXT: ret
%1 = add i32 %a, 4
ret i32 %1
}
define signext i32 @sext_addiw_sext(i32 signext %a) nounwind {
-; RV64I-LABEL: sext_addiw_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addiw a0, a0, 5
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_addiw_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: addiw a0, a0, 5
+; RV64-NEXT: ret
%1 = add i32 %a, 5
ret i32 %1
}
define signext i32 @sext_addiw_zext(i32 zeroext %a) nounwind {
-; RV64I-LABEL: sext_addiw_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addiw a0, a0, 6
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_addiw_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: addiw a0, a0, 6
+; RV64-NEXT: ret
%1 = add i32 %a, 6
ret i32 %1
}
@@ -1391,6 +1663,12 @@ define zeroext i32 @zext_addiw_aext(i32 %a) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_addiw_aext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: addiw a0, a0, 7
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = add i32 %a, 7
ret i32 %1
}
@@ -1402,6 +1680,12 @@ define zeroext i32 @zext_addiw_sext(i32 signext %a) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_addiw_sext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: addiw a0, a0, 8
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = add i32 %a, 8
ret i32 %1
}
@@ -1413,6 +1697,12 @@ define zeroext i32 @zext_addiw_zext(i32 zeroext %a) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_addiw_zext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: addiw a0, a0, 9
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = add i32 %a, 9
ret i32 %1
}
@@ -1420,55 +1710,55 @@ define zeroext i32 @zext_addiw_zext(i32 zeroext %a) nounwind {
; slliw should be selected whenever the return is signext.
define i32 @aext_slliw_aext(i32 %a) nounwind {
-; RV64I-LABEL: aext_slliw_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slliw a0, a0, 1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_slliw_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: slliw a0, a0, 1
+; RV64-NEXT: ret
%1 = shl i32 %a, 1
ret i32 %1
}
define i32 @aext_slliw_sext(i32 signext %a) nounwind {
-; RV64I-LABEL: aext_slliw_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slliw a0, a0, 2
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_slliw_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: slliw a0, a0, 2
+; RV64-NEXT: ret
%1 = shl i32 %a, 2
ret i32 %1
}
define i32 @aext_slliw_zext(i32 zeroext %a) nounwind {
-; RV64I-LABEL: aext_slliw_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slliw a0, a0, 3
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_slliw_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: slliw a0, a0, 3
+; RV64-NEXT: ret
%1 = shl i32 %a, 3
ret i32 %1
}
define signext i32 @sext_slliw_aext(i32 %a) nounwind {
-; RV64I-LABEL: sext_slliw_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slliw a0, a0, 4
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_slliw_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: slliw a0, a0, 4
+; RV64-NEXT: ret
%1 = shl i32 %a, 4
ret i32 %1
}
define signext i32 @sext_slliw_sext(i32 signext %a) nounwind {
-; RV64I-LABEL: sext_slliw_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slliw a0, a0, 5
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_slliw_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: slliw a0, a0, 5
+; RV64-NEXT: ret
%1 = shl i32 %a, 5
ret i32 %1
}
define signext i32 @sext_slliw_zext(i32 zeroext %a) nounwind {
-; RV64I-LABEL: sext_slliw_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slliw a0, a0, 6
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_slliw_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: slliw a0, a0, 6
+; RV64-NEXT: ret
%1 = shl i32 %a, 6
ret i32 %1
}
@@ -1481,6 +1771,12 @@ define zeroext i32 @zext_slliw_aext(i32 %a) nounwind {
; RV64I-NEXT: slli a0, a0, 39
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_slliw_aext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: slliw a0, a0, 7
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = shl i32 %a, 7
ret i32 %1
}
@@ -1491,6 +1787,12 @@ define zeroext i32 @zext_slliw_sext(i32 signext %a) nounwind {
; RV64I-NEXT: slli a0, a0, 40
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_slliw_sext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: slliw a0, a0, 8
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = shl i32 %a, 8
ret i32 %1
}
@@ -1501,6 +1803,12 @@ define zeroext i32 @zext_slliw_zext(i32 zeroext %a) nounwind {
; RV64I-NEXT: slli a0, a0, 41
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_slliw_zext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: slliw a0, a0, 9
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = shl i32 %a, 9
ret i32 %1
}
@@ -1509,82 +1817,82 @@ define zeroext i32 @zext_slliw_zext(i32 zeroext %a) nounwind {
; equivalent.
define i32 @aext_srliw_aext(i32 %a) nounwind {
-; RV64I-LABEL: aext_srliw_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srliw a0, a0, 1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_srliw_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: srliw a0, a0, 1
+; RV64-NEXT: ret
%1 = lshr i32 %a, 1
ret i32 %1
}
define i32 @aext_srliw_sext(i32 signext %a) nounwind {
-; RV64I-LABEL: aext_srliw_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srliw a0, a0, 2
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_srliw_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: srliw a0, a0, 2
+; RV64-NEXT: ret
%1 = lshr i32 %a, 2
ret i32 %1
}
define i32 @aext_srliw_zext(i32 zeroext %a) nounwind {
-; RV64I-LABEL: aext_srliw_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srli a0, a0, 3
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_srliw_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: srli a0, a0, 3
+; RV64-NEXT: ret
%1 = lshr i32 %a, 3
ret i32 %1
}
define signext i32 @sext_srliw_aext(i32 %a) nounwind {
-; RV64I-LABEL: sext_srliw_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srliw a0, a0, 4
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_srliw_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: srliw a0, a0, 4
+; RV64-NEXT: ret
%1 = lshr i32 %a, 4
ret i32 %1
}
define signext i32 @sext_srliw_sext(i32 signext %a) nounwind {
-; RV64I-LABEL: sext_srliw_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srliw a0, a0, 5
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_srliw_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: srliw a0, a0, 5
+; RV64-NEXT: ret
%1 = lshr i32 %a, 5
ret i32 %1
}
define signext i32 @sext_srliw_zext(i32 zeroext %a) nounwind {
-; RV64I-LABEL: sext_srliw_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srli a0, a0, 6
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_srliw_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: srli a0, a0, 6
+; RV64-NEXT: ret
%1 = lshr i32 %a, 6
ret i32 %1
}
define zeroext i32 @zext_srliw_aext(i32 %a) nounwind {
-; RV64I-LABEL: zext_srliw_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srliw a0, a0, 7
-; RV64I-NEXT: ret
+; RV64-LABEL: zext_srliw_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: srliw a0, a0, 7
+; RV64-NEXT: ret
%1 = lshr i32 %a, 7
ret i32 %1
}
define zeroext i32 @zext_srliw_sext(i32 signext %a) nounwind {
-; RV64I-LABEL: zext_srliw_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srliw a0, a0, 8
-; RV64I-NEXT: ret
+; RV64-LABEL: zext_srliw_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: srliw a0, a0, 8
+; RV64-NEXT: ret
%1 = lshr i32 %a, 8
ret i32 %1
}
define zeroext i32 @zext_srliw_zext(i32 zeroext %a) nounwind {
-; RV64I-LABEL: zext_srliw_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srli a0, a0, 9
-; RV64I-NEXT: ret
+; RV64-LABEL: zext_srliw_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: srli a0, a0, 9
+; RV64-NEXT: ret
%1 = lshr i32 %a, 9
ret i32 %1
}
@@ -1592,59 +1900,60 @@ define zeroext i32 @zext_srliw_zext(i32 zeroext %a) nounwind {
; srai is equivalent to sraiw if the first operand is sign-extended.
define i32 @aext_sraiw_aext(i32 %a) nounwind {
-; RV64I-LABEL: aext_sraiw_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraiw a0, a0, 1
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_sraiw_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraiw a0, a0, 1
+; RV64-NEXT: ret
%1 = ashr i32 %a, 1
ret i32 %1
}
define i32 @aext_sraiw_sext(i32 signext %a) nounwind {
-; RV64I-LABEL: aext_sraiw_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srai a0, a0, 2
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_sraiw_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: srai a0, a0, 2
+; RV64-NEXT: ret
%1 = ashr i32 %a, 2
ret i32 %1
}
define i32 @aext_sraiw_zext(i32 zeroext %a) nounwind {
-; RV64I-LABEL: aext_sraiw_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraiw a0, a0, 3
-; RV64I-NEXT: ret
+; RV64-LABEL: aext_sraiw_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraiw a0, a0, 3
+; RV64-NEXT: ret
%1 = ashr i32 %a, 3
ret i32 %1
}
define signext i32 @sext_sraiw_aext(i32 %a) nounwind {
-; RV64I-LABEL: sext_sraiw_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraiw a0, a0, 4
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_sraiw_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraiw a0, a0, 4
+; RV64-NEXT: ret
%1 = ashr i32 %a, 4
ret i32 %1
}
define signext i32 @sext_sraiw_sext(i32 signext %a) nounwind {
-; RV64I-LABEL: sext_sraiw_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srai a0, a0, 5
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_sraiw_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: srai a0, a0, 5
+; RV64-NEXT: ret
%1 = ashr i32 %a, 5
ret i32 %1
}
define signext i32 @sext_sraiw_zext(i32 zeroext %a) nounwind {
-; RV64I-LABEL: sext_sraiw_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sraiw a0, a0, 6
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_sraiw_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: sraiw a0, a0, 6
+; RV64-NEXT: ret
%1 = ashr i32 %a, 6
ret i32 %1
}
+; TODO: The sext.w+srli can be replaced with sraiw with Zba.
define zeroext i32 @zext_sraiw_aext(i32 %a) nounwind {
; RV64I-LABEL: zext_sraiw_aext:
; RV64I: # %bb.0:
@@ -1652,6 +1961,13 @@ define zeroext i32 @zext_sraiw_aext(i32 %a) nounwind {
; RV64I-NEXT: slli a0, a0, 25
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sraiw_aext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sext.w a0, a0
+; RV64ZBA-NEXT: srli a0, a0, 7
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = ashr i32 %a, 7
ret i32 %1
}
@@ -1662,10 +1978,17 @@ define zeroext i32 @zext_sraiw_sext(i32 signext %a) nounwind {
; RV64I-NEXT: slli a0, a0, 24
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sraiw_sext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: srli a0, a0, 8
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = ashr i32 %a, 8
ret i32 %1
}
+; TODO: The sext.w+srli can be replaced with sraiw with Zba.
define zeroext i32 @zext_sraiw_zext(i32 zeroext %a) nounwind {
; RV64I-LABEL: zext_sraiw_zext:
; RV64I: # %bb.0:
@@ -1673,6 +1996,13 @@ define zeroext i32 @zext_sraiw_zext(i32 zeroext %a) nounwind {
; RV64I-NEXT: slli a0, a0, 23
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sraiw_zext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sext.w a0, a0
+; RV64ZBA-NEXT: srli a0, a0, 9
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = ashr i32 %a, 9
ret i32 %1
}
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