[PATCH] D109110: [RISCV] Split PseudoVSETVLI into 2 instructions to allow different register classes for rs1.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.

Well, I can't think of much to comment on here. I do think this is the "right" thing to do. Thanks again for solving this issue.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109110/new/

https://reviews.llvm.org/D109110