[llvm] 4b04d54 - [RISCV] Fix typo in RISCVSchedSiFive7.td

[Evandro Menezes via llvm-commits]

Author: Alexander Pivovarov
Date: 2021-09-01T16:39:48-05:00
New Revision: 4b04d54206a5b7f549af9a2f0a9588ee8e933eb2

URL: https://github.com/llvm/llvm-project/commit/4b04d54206a5b7f549af9a2f0a9588ee8e933eb2
DIFF: https://github.com/llvm/llvm-project/commit/4b04d54206a5b7f549af9a2f0a9588ee8e933eb2.diff

LOG: [RISCV] Fix typo in RISCVSchedSiFive7.td

Fix typo in "microarchitecure".

Differential Revision: https://reviews.llvm.org/D109006

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 75ca6ca861be..5b435fcb16a2 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -18,7 +18,7 @@ def SiFive7Model : SchedMachineModel {
   let UnsupportedFeatures = [HasStdExtV, HasStdExtZvamo, HasStdExtZvlsseg];
 }
 
-// The SiFive7 microarchitecure has two pipelines: A and B.
+// The SiFive7 microarchitecture has two pipelines: A and B.
 // Pipe A can handle memory, integer alu and vector operations.
 // Pipe B can handle integer alu, control flow, integer multiply and divide,
 // and floating point computation.