[llvm] 0022426 - [AMDGPU] Update Call Convention docs for GFX90A
Scott Linder via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 1 13:03:27 PDT 2021
Author: Scott Linder
Date: 2021-09-01T20:02:41Z
New Revision: 0022426917e3cf5e6bb55ba691bea67094663114
URL: https://github.com/llvm/llvm-project/commit/0022426917e3cf5e6bb55ba691bea67094663114
DIFF: https://github.com/llvm/llvm-project/commit/0022426917e3cf5e6bb55ba691bea67094663114.diff
LOG: [AMDGPU] Update Call Convention docs for GFX90A
Document the CSR AGPRs for GFX90A.
Remove the TODO for gfx908, as the answer is that we don't mark any
AGPRs as callee-saved except for GFX90A, i.e. the docs as-is are correct
for gfx908.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D109009
Added:
Modified:
llvm/docs/AMDGPUUsage.rst
Removed:
################################################################################
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 51c4e9e1bb256..5d197d8b4373e 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -10835,6 +10835,7 @@ On exit from a function:
registers are intermixed at regular intervals in order to keep a
similar ratio independent of the number of allocated VGPRs.
+ * GFX90A: All AGPR registers except the clobbered registers AGPR0-31.
* Lanes of all VGPRs that are inactive at the call site.
For the AMDGPU backend, an inter-procedural register allocation (IPRA)
@@ -10850,8 +10851,6 @@ On exit from a function:
.. TODO::
- - On gfx908 are all ACC registers clobbered?
-
- How are function results returned? The address of structured types is passed
by reference, but what about other types?
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