[PATCH] D109052: [AMDGPU][GlobalISel] Fix waterfall loops

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp:754
+      // If the mapping changed the control flow, look at the new successors.
+      for (auto *Suc : MBB->successors()) {
+        if (!OrigBlocks.count(Suc)) {
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2 c's


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp:906
                               bool IsTailCall) {
-  return IsTailCall ? AMDGPU::SI_TCRETURN : AMDGPU::SI_CALL;
+  return IsTailCall ? AMDGPU::SI_TCRETURN : AMDGPU::G_SI_CALL;
 }
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I think in the absence of knowing if the call target is uniform in CallLowering, we can't do tail calls


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Comment at: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp:3142-3146
+    while (Start->getOpcode() != FrameSetupOpcode)
+      --Start;
+    MachineBasicBlock::iterator End(&MI);
+    while (End->getOpcode() != FrameDestroyOpcode)
+      ++End;
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I'm not sure you can guarantee this is the range that needs to be moved. Could other instructions have been moved across these between the IRTranslator and here?


Repository:
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  https://reviews.llvm.org/D109052/new/

https://reviews.llvm.org/D109052