[PATCH] D108522: [X86][SSE] combineMulToPMADDWD - improve recognition of sign/zero extended upper bits

[Pengfei Wang via Phabricator via llvm-commits]

pengfei accepted this revision.
pengfei added a comment.
This revision is now accepted and ready to land.

The math looks good to me.
Wild thought: can we extend to zero/signed bits = 16 if the other element has more than 17 bits zero/signed? I think this should be common as a sext/zext <2 x i16> to <2 x i32>.



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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:51613
 
+// Simplify VPMADDWD operations.
+static SDValue combineVPMADDWD(SDNode *N, SelectionDAG &DAG,
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Is there a test to cover this combine?


Repository:
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  https://reviews.llvm.org/D108522/new/

https://reviews.llvm.org/D108522