[PATCH] D105612: [PowerPC] Implement quadword atomic load/store

[Kai Luo via Phabricator via llvm-commits]

lkail marked 3 inline comments as done.
lkail added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:17363
   if (MemVT.isScalarInteger()) {
-    assert(Size <= 64 && "Not expecting scalar integers larger than 8 bytes!");
+    assert(Size <= 128 &&
+           "Not expecting scalar integers larger than 16 bytes!");
----------------
jsji wrote:
> So we will set Flag to `PPC::MOF_DoubleWordInt` for 128.  Although we haven't used the flags for now, I think it would be better if we add one more flag for 128?
Good catch. I'll add TODO at `PPCTargetLowering::initializeAddrModeMap` and address it with following patches.


================
Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:3106
 
+    // FIXME: Maybe we can expand it in 'PowerPC Expand Atomic' pass.
   case PPC::CFENCE8: {
----------------
jsji wrote:
> nit: indent is off?
Already run `clang-format` on it, it should have matched `clang-format`'s behavior.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105612/new/

https://reviews.llvm.org/D105612