[llvm] a78dd72 - [SLP][RISCV] Implement unsigned getMinVectorRegisterBitWidth() for RISCV

[via llvm-commits]

Author: Luke
Date: 2021-09-01T14:25:15+08:00
New Revision: a78dd726f46de63529585b2569314d35ce39105d

URL: https://github.com/llvm/llvm-project/commit/a78dd726f46de63529585b2569314d35ce39105d
DIFF: https://github.com/llvm/llvm-project/commit/a78dd726f46de63529585b2569314d35ce39105d.diff

LOG: [SLP][RISCV] Implement unsigned getMinVectorRegisterBitWidth() for RISCV

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D108973

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index 4853351ececa8..b1d0e386f9926 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -73,6 +73,10 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
     llvm_unreachable("Unsupported register kind");
   }
 
+  unsigned getMinVectorRegisterBitWidth() const {
+    return ST->hasStdExtV() ? ST->getMinRVVVectorSizeInBits() : 0;
+  }
+
   InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
                                          const Value *Ptr, bool VariableMask,
                                          Align Alignment,