[llvm] 6a75041 - [TableGen] Allow target specific flags for RegisterClass
Christudasan Devadasan via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 31 19:40:11 PDT 2021
Author: Christudasan Devadasan
Date: 2021-08-31T22:29:11-04:00
New Revision: 6a75041a1614af1ca787af5a18ea9ddbe4dd5c16
URL: https://github.com/llvm/llvm-project/commit/6a75041a1614af1ca787af5a18ea9ddbe4dd5c16
DIFF: https://github.com/llvm/llvm-project/commit/6a75041a1614af1ca787af5a18ea9ddbe4dd5c16.diff
LOG: [TableGen] Allow target specific flags for RegisterClass
Analogous to the TSFlags for machine instructions, this
patch introduces a bit vector for register classes to have
target specific flags that become a tablegened value in
TargetRegisterClass.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D108767
Added:
llvm/test/TableGen/RegisterInfoEmitter-tsflags.td
Modified:
llvm/include/llvm/CodeGen/TargetRegisterInfo.h
llvm/include/llvm/Target/Target.td
llvm/utils/TableGen/CodeGenRegisters.cpp
llvm/utils/TableGen/CodeGenRegisters.h
llvm/utils/TableGen/RegisterInfoEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 70017173a0de3..8483d078ca74f 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -57,6 +57,8 @@ class TargetRegisterClass {
/// Classes with a higher priority value are assigned first by register
/// allocators using a greedy heuristic. The value is in the range [0,63].
const uint8_t AllocationPriority;
+ /// Configurable target specific flags.
+ const uint8_t TSFlags;
/// Whether the class supports two (or more) disjunct subregister indices.
const bool HasDisjunctSubRegs;
/// Whether a combination of subregisters can cover every register in the
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index e9720d7651677..d70df3936e9f4 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -306,6 +306,9 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
// the assembly matcher will provide a function to map from diagnostic types
// to message strings.
string DiagnosticString = "";
+
+ // Target-specific flags. This becomes the TSFlags field in TargetRegisterClass.
+ bits<8> TSFlags = 0;
}
// The memberList in a RegisterClass is a dag of set operations. TableGen
diff --git a/llvm/test/TableGen/RegisterInfoEmitter-tsflags.td b/llvm/test/TableGen/RegisterInfoEmitter-tsflags.td
new file mode 100644
index 0000000000000..55db3ddb1f27e
--- /dev/null
+++ b/llvm/test/TableGen/RegisterInfoEmitter-tsflags.td
@@ -0,0 +1,48 @@
+// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
+
+// Configure and test TSFlags for a target.
+include "llvm/Target/Target.td"
+
+let Namespace = "MyTarget" in {
+ def R : Register<"r">;
+ def D : Register<"d">;
+ def S : Register<"s">;
+}
+
+class MyClass <int size, list<ValueType> types, dag regList>
+ : RegisterClass <"MyTarget", types, size, regList> {
+ // Define the target bitfields.
+ field bit A = 0;
+ field bits<2> B = 0;
+
+ // Associate the defined bitfields to unique bit positions in TSFlags.
+ let TSFlags{0} = A;
+ let TSFlags{2-1} = B;
+}
+
+// Default value for TSFlags.
+def MyRegs : MyClass<32, [i32], (add R)>;
+
+def SRegs : MyClass<32, [i32], (add S)> {
+ let A = 1;
+}
+
+def DRegs : MyClass<32, [i32], (add D)>{
+ let B = 3;
+}
+
+def SDRegs : MyClass<32, [i32], (add D, S)>{
+ let A = 1;
+ let B = 3;
+}
+
+def MyTarget : Target;
+
+// CHECK: extern const TargetRegisterClass SDRegsRegClass = {
+// CHECK: 0x07, /* TSFlags */
+// CHECK: extern const TargetRegisterClass DRegsRegClass = {
+// CHECK: 0x06, /* TSFlags */
+// CHECK: extern const TargetRegisterClass MyRegsRegClass = {
+// CHECK: 0x00, /* TSFlags */
+// CHECK: extern const TargetRegisterClass SRegsRegClass = {
+// CHECK: 0x01, /* TSFlags */
diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp
index 930b7742103eb..0392388c7f777 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -734,7 +734,7 @@ static void sortAndUniqueRegisters(CodeGenRegister::Vec &M) {
CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
: TheDef(R), Name(std::string(R->getName())),
- TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1) {
+ TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1), TSFlags(0) {
GeneratePressureSet = R->getValueAsBit("GeneratePressureSet");
std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
if (TypeList.empty())
@@ -802,6 +802,12 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
if (AllocationPriority < 0 || AllocationPriority > 63)
PrintFatalError(R->getLoc(), "AllocationPriority out of range [0,63]");
this->AllocationPriority = AllocationPriority;
+
+ BitsInit *TSF = R->getValueAsBitsInit("TSFlags");
+ for (unsigned I = 0, E = TSF->getNumBits(); I != E; ++I) {
+ BitInit *Bit = cast<BitInit>(TSF->getBit(I));
+ TSFlags |= uint8_t(Bit->getValue()) << I;
+ }
}
// Create an inferred register class that was missing from the .td files.
@@ -811,7 +817,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank,
StringRef Name, Key Props)
: Members(*Props.Members), TheDef(nullptr), Name(std::string(Name)),
TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1), RSI(Props.RSI),
- CopyCost(0), Allocatable(true), AllocationPriority(0) {
+ CopyCost(0), Allocatable(true), AllocationPriority(0), TSFlags(0) {
Artificial = true;
GeneratePressureSet = false;
for (const auto R : Members) {
@@ -839,6 +845,7 @@ void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) {
});
AltOrderSelect = Super.AltOrderSelect;
AllocationPriority = Super.AllocationPriority;
+ TSFlags = Super.TSFlags;
GeneratePressureSet |= Super.GeneratePressureSet;
// Copy all allocation orders, filter out foreign registers from the larger
diff --git a/llvm/utils/TableGen/CodeGenRegisters.h b/llvm/utils/TableGen/CodeGenRegisters.h
index 6a0696011a408..c9fcf83b0a8a0 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/CodeGenRegisters.h
@@ -332,6 +332,7 @@ namespace llvm {
bool Allocatable;
StringRef AltOrderSelect;
uint8_t AllocationPriority;
+ uint8_t TSFlags;
/// Contains the combination of the lane masks of all subregisters.
LaneBitmask LaneMask;
/// True if there are at least 2 subregisters which do not interfere.
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 037fad207ac7e..1ed7bc103f9ce 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -1411,6 +1411,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
<< SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n ";
printMask(OS, RC.LaneMask);
OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n "
+ << format("0x%02x", RC.TSFlags) << ", /* TSFlags */\n "
<< (RC.HasDisjunctSubRegs?"true":"false")
<< ", /* HasDisjunctSubRegs */\n "
<< (RC.CoveredBySubRegs?"true":"false")
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