[llvm] 74043ca - [X86] Enable half type support in inline assembly constraints
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Tue Aug 31 18:29:42 PDT 2021
Author: Wang, Pengfei
Date: 2021-09-01T09:29:31+08:00
New Revision: 74043caef2eec37600570706d6bb5515bff9436f
URL: https://github.com/llvm/llvm-project/commit/74043caef2eec37600570706d6bb5515bff9436f
DIFF: https://github.com/llvm/llvm-project/commit/74043caef2eec37600570706d6bb5515bff9436f.diff
LOG: [X86] Enable half type support in inline assembly constraints
Reviewed By: LuoYuanke
Differential Revision: https://reviews.llvm.org/D105799
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index a97fc71969c7e..17fd32e3898df 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -53115,6 +53115,10 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
switch (VT.SimpleTy) {
default: break;
// Scalar SSE types.
+ case MVT::f16:
+ if (VConstraint && Subtarget.hasFP16())
+ return std::make_pair(0U, &X86::FR16XRegClass);
+ break;
case MVT::f32:
case MVT::i32:
if (VConstraint && Subtarget.hasVLX())
@@ -53133,6 +53137,10 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
}
break;
// Vector types and fp128.
+ case MVT::v8f16:
+ if (!Subtarget.hasFP16())
+ break;
+ LLVM_FALLTHROUGH;
case MVT::f128:
case MVT::v16i8:
case MVT::v8i16:
@@ -53144,6 +53152,10 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
return std::make_pair(0U, &X86::VR128XRegClass);
return std::make_pair(0U, &X86::VR128RegClass);
// AVX types.
+ case MVT::v16f16:
+ if (!Subtarget.hasFP16())
+ break;
+ LLVM_FALLTHROUGH;
case MVT::v32i8:
case MVT::v16i16:
case MVT::v8i32:
@@ -53155,6 +53167,10 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
if (Subtarget.hasAVX())
return std::make_pair(0U, &X86::VR256RegClass);
break;
+ case MVT::v32f16:
+ if (!Subtarget.hasFP16())
+ break;
+ LLVM_FALLTHROUGH;
case MVT::v64i8:
case MVT::v32i16:
case MVT::v8f64:
@@ -53184,12 +53200,20 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
switch (VT.SimpleTy) {
default: break;
// Scalar SSE types.
+ case MVT::f16:
+ if (!Subtarget.hasFP16())
+ break;
+ return std::make_pair(X86::XMM0, &X86::FR16XRegClass);
case MVT::f32:
case MVT::i32:
return std::make_pair(X86::XMM0, &X86::FR32RegClass);
case MVT::f64:
case MVT::i64:
return std::make_pair(X86::XMM0, &X86::FR64RegClass);
+ case MVT::v8f16:
+ if (!Subtarget.hasFP16())
+ break;
+ LLVM_FALLTHROUGH;
case MVT::f128:
case MVT::v16i8:
case MVT::v8i16:
@@ -53199,6 +53223,10 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
case MVT::v2f64:
return std::make_pair(X86::XMM0, &X86::VR128RegClass);
// AVX types.
+ case MVT::v16f16:
+ if (!Subtarget.hasFP16())
+ break;
+ LLVM_FALLTHROUGH;
case MVT::v32i8:
case MVT::v16i16:
case MVT::v8i32:
@@ -53208,6 +53236,10 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
if (Subtarget.hasAVX())
return std::make_pair(X86::YMM0, &X86::VR256RegClass);
break;
+ case MVT::v32f16:
+ if (!Subtarget.hasFP16())
+ break;
+ LLVM_FALLTHROUGH;
case MVT::v64i8:
case MVT::v32i16:
case MVT::v8f64:
@@ -53365,7 +53397,9 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
// find, ignoring the required type.
// TODO: Handle f128 and i128 in FR128RegClass after it is tested well.
- if (VT == MVT::f32 || VT == MVT::i32)
+ if (VT == MVT::f16)
+ Res.second = &X86::FR16XRegClass;
+ else if (VT == MVT::f32 || VT == MVT::i32)
Res.second = &X86::FR32XRegClass;
else if (VT == MVT::f64 || VT == MVT::i64)
Res.second = &X86::FR64XRegClass;
diff --git a/llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll b/llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
index cc647d2ba7715..fcea55c47cd3e 100644
--- a/llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
+++ b/llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
@@ -1,5 +1,9 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f -stop-after=finalize-isel | FileCheck %s
+; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f -stop-after=finalize-isel > %t 2> %t.err
+; RUN: FileCheck < %t %s
+; RUN: FileCheck --check-prefix=CHECK-STDERR < %t.err %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512fp16 -stop-after=finalize-isel | FileCheck --check-prefixes=CHECK,FP16 %s
+; CHECK-LABEL: name: mask_Yk_i8
; CHECK: %[[REG1:.*]]:vr512_0_15 = COPY %1
; CHECK: %[[REG2:.*]]:vr512_0_15 = COPY %2
; CHECK: INLINEASM &"vpaddq\09$3, $2, $0 {$1}", 0 /* attdialect */, {{.*}}, def %{{.*}}, {{.*}}, %{{.*}}, {{.*}}, %[[REG1]], {{.*}}, %[[REG2]], 12 /* clobber */, implicit-def early-clobber $df, 12 /* clobber */, implicit-def early-clobber $fpsw, 12 /* clobber */, implicit-def early-clobber $eflags
@@ -9,3 +13,14 @@ entry:
%0 = tail call <8 x i64> asm "vpaddq\09$3, $2, $0 {$1}", "=x,^Yk,x,x,~{dirflag},~{fpsr},~{flags}"(i8 %msk, <8 x i64> %x, <8 x i64> %y)
ret <8 x i64> %0
}
+
+; FP16-LABEL: name: mask_Yk_f16
+; FP16: %[[REG1:.*]]:vr512_0_15 = COPY %1
+; FP16: %[[REG2:.*]]:vr512_0_15 = COPY %2
+; FP16: INLINEASM &"vaddph\09$3, $2, $0 {$1}", 0 /* attdialect */, {{.*}}, def %{{.*}}, {{.*}}, %{{.*}}, {{.*}}, %[[REG1]], {{.*}}, %[[REG2]], 12 /* clobber */, implicit-def early-clobber $df, 12 /* clobber */, implicit-def early-clobber $fpsw, 12 /* clobber */, implicit-def early-clobber $eflags
+; CHECK-STDERR: couldn't allocate output register for constraint 'x'
+define <32 x half> @mask_Yk_f16(i8 signext %msk, <32 x half> %x, <32 x half> %y) {
+entry:
+ %0 = tail call <32 x half> asm "vaddph\09$3, $2, $0 {$1}", "=x,^Yk,x,x,~{dirflag},~{fpsr},~{flags}"(i8 %msk, <32 x half> %x, <32 x half> %y)
+ ret <32 x half> %0
+}
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