[PATCH] D108815: [AMDGPU] Introduce RC flags for vector register classes
Stanislav Mekhanoshin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 31 10:28:51 PDT 2021
rampitec added inline comments.
================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:2169
-// TODO: It might be helpful to have some target specific flags in
-// TargetRegisterClass to mark which classes are VGPRs to make this trivial.
bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
+ return RC->TSFlags & SIRCFlags::IsVGPR;
----------------
rampitec wrote:
> I think we need a comment here it only works with an allocatable class until we need to change it to work with combined classes.
Not here, actually. That is isVGPRClass would be broken if given a VS class. So it seems we will need a flag for SGPRs and check all 3 flags. Not in this patch.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D108815/new/
https://reviews.llvm.org/D108815
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