[llvm] 94d3ff0 - [GlobalISel] Don't use G_FPTOSI in G_ISNAN legalization

[Jessica Paquette via llvm-commits]

Author: Jessica Paquette
Date: 2021-08-31T10:26:42-07:00
New Revision: 94d3ff09cfa8d7aecf480e54da9a5334e262e76b

URL: https://github.com/llvm/llvm-project/commit/94d3ff09cfa8d7aecf480e54da9a5334e262e76b
DIFF: https://github.com/llvm/llvm-project/commit/94d3ff09cfa8d7aecf480e54da9a5334e262e76b.diff

LOG: [GlobalISel] Don't use G_FPTOSI in G_ISNAN legalization

As noted in the comments in D108227, using G_FPTOSI produces wrong results for
G_ISNAN. Drop the G_FPTOSI and perform the operation on integer types.

Elsewhere in LLVM, a bitcast would be the appropriate choice (as it is in SDAG).
GlobalISel does not distinguish between integer and FP types, so a bitcast would
be meaningless here.

Added: 
    

Modified: 
    llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/legalize-isnan.mir

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 463437a4db088..454430e4c03db 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -7420,10 +7420,9 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerIsNaN(MachineInstr &MI) {
 
   // NaN has all exp bits set and a non zero significand. Therefore:
   // isnan(V) == exp mask < abs(V)
-  auto FPToSI = MIRBuilder.buildFPTOSI(SrcTy, Src);
   auto Mask = APInt::getSignedMaxValue(SrcTy.getScalarSizeInBits());
   auto MaskCst = MIRBuilder.buildConstant(SrcTy, Mask);
-  auto AbsV = MIRBuilder.buildAnd(SrcTy, FPToSI, MaskCst);
+  auto AbsV = MIRBuilder.buildAnd(SrcTy, Src, MaskCst);
   auto *FloatTy = getFloatTypeForLLT(MI.getMF()->getFunction().getContext(),
                                      SrcTy.getScalarType());
   if (!FloatTy)

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-isnan.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-isnan.mir
index 4fedb2fe95280..fee22e15c25df 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-isnan.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-isnan.mir
@@ -61,10 +61,9 @@ body:             |
     ; CHECK-LABEL: name: scalar_no_flags
     ; CHECK: liveins: $h0
     ; CHECK: %val:_(s16) = COPY $h0
-    ; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %val(s16)
-    ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](s32)
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %val(s16)
     ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
-    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[FPTOSI]], [[C]]
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
     ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31744
     ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[AND]], 16
     ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[C1]](s32), [[SEXT_INREG]]
@@ -89,16 +88,13 @@ body:             |
     ; CHECK-LABEL: name: vector_no_flags
     ; CHECK: liveins: $d0
     ; CHECK: %val:_(<4 x s16>) = COPY $d0
-    ; CHECK: [[FPTOSI:%[0-9]+]]:_(<4 x s16>) = G_FPTOSI %val(<4 x s16>)
     ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
     ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16)
-    ; CHECK: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[FPTOSI]], [[BUILD_VECTOR]]
+    ; CHECK: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND %val, [[BUILD_VECTOR]]
     ; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 31744
     ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[C1]](s16), [[C1]](s16), [[C1]](s16), [[C1]](s16)
     ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(slt), [[BUILD_VECTOR1]](<4 x s16>), [[AND]]
-    ; CHECK: %isnan:_(<4 x s1>) = G_TRUNC [[ICMP]](<4 x s16>)
-    ; CHECK: %ext:_(<4 x s16>) = G_ANYEXT %isnan(<4 x s1>)
-    ; CHECK: $d0 = COPY %ext(<4 x s16>)
+    ; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
     ; CHECK: RET_ReallyLR implicit $d0
     %val:_(<4 x s16>) = COPY $d0
     %isnan:_(<4 x s1>) = G_ISNAN %val(<4 x s16>)