[PATCH] D108227: [GlobalISel] Implement lowering for G_ISNAN + use it in AArch64

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham added inline comments.


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Comment at: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:7378
+  // isnan(V) == exp mask < abs(V)
+  auto FPToSI = MIRBuilder.buildFPTOSI(SrcTy, Src);
+  auto Mask = APInt::getSignedMaxValue(SrcTy.getScalarSizeInBits());
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Sorry to be late spotting this, but I think this `fptosi` can't be right. 

Surely what we need here is the integer that represents the //encoding// of the FP number, with sign, exponent and mantissa fields?

But this is computing the integer that represents its //numerical value//, as if from a source-level float→int conversion.

In the AArch64 output code I'm seeing, this `fptosi` is coming out as an `FCVTZS w8,s0` instruction, and with a sensible single-precision NaN in s0 (encoding 0x7fc00000), that instruction is generating zero in w8, which leads to isnan(NaN) returning false.

I don't speak good MIR, but surely something like a bitcast would be the right operation.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108227/new/

https://reviews.llvm.org/D108227