[llvm] aaae726 - [SLPVectorizer][Test] Add test for extractelements with (non)const indices (NFC)

[Anton Afanasyev via llvm-commits]

Author: Anton Afanasyev
Date: 2021-08-31T16:14:26+03:00
New Revision: aaae726afb0efdac9867972ec0c5d544a637407a

URL: https://github.com/llvm/llvm-project/commit/aaae726afb0efdac9867972ec0c5d544a637407a
DIFF: https://github.com/llvm/llvm-project/commit/aaae726afb0efdac9867972ec0c5d544a637407a.diff

LOG: [SLPVectorizer][Test] Add test for extractelements with (non)const indices (NFC)

Add test for an issue discussed here: https://reviews.llvm.org/D108703#2974289

Added: 
    llvm/test/Transforms/SLPVectorizer/X86/extract_with_non_const_index.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/SLPVectorizer/X86/extract_with_non_const_index.ll b/llvm/test/Transforms/SLPVectorizer/X86/extract_with_non_const_index.ll
new file mode 100644
index 000000000000..b723e4bbee80
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/extract_with_non_const_index.ll
@@ -0,0 +1,44 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -mtriple=x86_64-unknown -slp-vectorizer -S | FileCheck %s
+
+; Reproducer for an issue discussed here:
+; https://reviews.llvm.org/D108703#2974289
+
+define void @test([4 x float]* nocapture %o, [2 x float]* nocapture nonnull readonly dereferenceable(8) %a, [2 x float]* nocapture nonnull readonly dereferenceable(8) %b, i32 signext %component) {
+; CHECK-LABEL: @test(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = bitcast [2 x float]* [[A:%.*]] to <2 x float>*
+; CHECK-NEXT:    [[TMP1:%.*]] = load <2 x float>, <2 x float>* [[TMP0]], align 1
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast [2 x float]* [[B:%.*]] to <2 x float>*
+; CHECK-NEXT:    [[TMP3:%.*]] = load <2 x float>, <2 x float>* [[TMP2]], align 1
+; CHECK-NEXT:    [[TMP4:%.*]] = trunc i32 [[COMPONENT:%.*]] to i8
+; CHECK-NEXT:    [[TMP5:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 2, i32 3, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x float> [[TMP5]], i8 [[TMP4]]
+; CHECK-NEXT:    [[TMP7:%.*]] = insertelement <4 x float> undef, float [[TMP6]], i64 0
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <2 x float> [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP9:%.*]] = insertelement <4 x float> [[TMP7]], float [[TMP8]], i64 1
+; CHECK-NEXT:    [[TMP10:%.*]] = extractelement <2 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[TMP11:%.*]] = insertelement <4 x float> [[TMP9]], float [[TMP10]], i64 2
+; CHECK-NEXT:    [[TMP12:%.*]] = insertelement <4 x float> [[TMP11]], float [[TMP6]], i64 3
+; CHECK-NEXT:    [[TMP13:%.*]] = bitcast [4 x float]* [[O:%.*]] to <4 x float>*
+; CHECK-NEXT:    store <4 x float> [[TMP12]], <4 x float>* [[TMP13]], align 1
+; CHECK-NEXT:    ret void
+;
+entry:
+  %0 = bitcast [2 x float]* %a to <2 x float>*
+  %1 = load <2 x float>, <2 x float>* %0, align 1
+  %2 = bitcast [2 x float]* %b to <2 x float>*
+  %3 = load <2 x float>, <2 x float>* %2, align 1
+  %4 = trunc i32 %component to i8
+  %5 = shufflevector <2 x float> %1, <2 x float> %3, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 2, i32 3, i32 undef, i32 undef>
+  %6 = extractelement <8 x float> %5, i8 %4
+  %7 = insertelement <4 x float> undef, float %6, i64 0
+  %8 = extractelement <2 x float> %3, i32 1
+  %9 = insertelement <4 x float> %7, float %8, i64 1
+  %10 = extractelement <2 x float> %1, i32 1
+  %11 = insertelement <4 x float> %9, float %10, i64 2
+  %12 = insertelement <4 x float> %11, float %6, i64 3
+  %13 = bitcast [4 x float]* %o to <4 x float>*
+  store <4 x float> %12, <4 x float>* %13, align 1
+  ret void
+}