[PATCH] D108988: [ARM] Simplify address calculation for NEON load/store

[Andrew Savonichev via Phabricator via llvm-commits]

asavonic created this revision.
asavonic added reviewers: dmgreen, t.p.northover.
Herald added subscribers: ecnelises, arphaman, hiraditya, kristof.beyls, mgorny.
asavonic requested review of this revision.
Herald added a project: LLVM.
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The patch attempts to optimize a sequence of SIMD loads from the same
base pointer:

  %0 = gep float*, float* base, i32 4
  %1 = bitcast float* %0 to <4 x float>*
  %2 = load <4 x float>, <4 x float>* %1
  ...
  %n1 = gep float*, float* base, i32 N
  %n2 = bitcast float* %n1 to <4 x float>*
  %n3 = load <4 x float>, <4 x float>* %n2

For AArch64 the compiler generates a sequence of LDR Qt, [Xn, #16].
However, 32-bit NEON VLD1/VST1 lack the [Wn, #imm] addressing mode, so
the address is computed before every ld/st instruction:

  add r2, r0, #32
  add r0, r0, #16
  vld1.32 {d18, d19}, [r2]
  vld1.32 {d22, d23}, [r0]

This can be improved by computing address for the first load, and then
using a post-indexed form of VLD1/VST1 to load the rest:

  add r0, r0, #16
  vld1.32 {d18, d19}, [r0]!
  vld1.32 {d22, d23}, [r0]

In order to do that, the patch introduces a target-specific pass
operating on LLVM IR, which makes IR more post-indexing friendly and
lets the existing DAG optimization patterns to choose post-indexed
variants of VLD1/VST1. Some DAG transformations can break this by
reassociation, so it is conditionally disabled via
TLI.shouldRetainImmediatePostIncrement.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108988

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/ARM/ARM.h
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/ARM/ARMPostIndexingOptimizer.cpp
  llvm/lib/Target/ARM/ARMTargetMachine.cpp
  llvm/lib/Target/ARM/CMakeLists.txt
  llvm/test/CodeGen/ARM/O3-pipeline.ll
  llvm/test/CodeGen/ARM/arm-post-indexing-opt.ll
  llvm/test/CodeGen/ARM/misched-fusion-aes.ll
  llvm/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll

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