[llvm] f417b66 - [Arm] Add assert in T2 Imm7s code emitter

[Simon Wallis via llvm-commits]

Author: Simon Wallis
Date: 2021-08-31T08:16:48+01:00
New Revision: f417b660eefd512b0058be4aab64180b9a5ee512

URL: https://github.com/llvm/llvm-project/commit/f417b660eefd512b0058be4aab64180b9a5ee512
DIFF: https://github.com/llvm/llvm-project/commit/f417b660eefd512b0058be4aab64180b9a5ee512.diff

LOG: [Arm] Add assert in T2 Imm7s code emitter

Add assert to provoke failure in object file output, not just in disassembly output.

Reviewed By: yroux

Differential Revision: https://reviews.llvm.org/D107259

Added: 
    

Modified: 
    llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index ced48ccc98834..5ecacdab390f0 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -1138,6 +1138,7 @@ getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
   // representation for the complex operand in the .td file. This isn't just
   // style, unfortunately. As-is, we can't represent the distinct encoding
   // for #-0.
+  assert(((Imm8 & 0x3) == 0) && "Not a valid immediate!");
   uint32_t Binary = (Imm8 >> 2) & 0xff;
   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
   if (isAdd)