[PATCH] D108857: Fix typo in comments

[Shivam Gupta via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGeb946cc5b66c: Fix typo in comments (authored by apivovarov, committed by xgupta).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108857/new/

https://reviews.llvm.org/D108857

Files:
  llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def
  llvm/include/llvm/Target/TargetOptions.h
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -3010,7 +3010,7 @@
             .addReg(SrcVSR + VecNo)
             .addReg(SrcVSR + VecNo);
     }
-    // BUILD_UACC is expanded to 4 copies of the underlying vsx regisers.
+    // BUILD_UACC is expanded to 4 copies of the underlying vsx registers.
     // So after building the 4 copies, we can replace the BUILD_UACC instruction
     // with a NOP.
     LLVM_FALLTHROUGH;
Index: llvm/include/llvm/Target/TargetOptions.h
===================================================================
--- llvm/include/llvm/Target/TargetOptions.h
+++ llvm/include/llvm/Target/TargetOptions.h
@@ -174,7 +174,7 @@
 
     /// EnableAIXExtendedAltivecABI - This flag returns true when -vec-extabi is
     /// specified. The code generator is then able to use both volatile and
-    /// nonvolitle vector regisers. When false, the code generator only uses
+    /// nonvolitle vector registers. When false, the code generator only uses
     /// volatile vector registers which is the default setting on AIX.
     unsigned EnableAIXExtendedAltivecABI : 1;
 
Index: llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def
===================================================================
--- llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def
+++ llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def
@@ -373,7 +373,7 @@
 
 CV_REGISTER(ARM_NOREG, 0)
 
-// General purpose 32-bit integer regisers
+// General purpose 32-bit integer registers
 
 CV_REGISTER(ARM_R0, 10)
 CV_REGISTER(ARM_R1, 11)


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