[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0-rc1 spec

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D108694#2971960 <https://reviews.llvm.org/D108694#2971960>, @frasercrmck wrote:

> I also don't think we're ready/able to support `Zvl32b` for the reasons stated above. I think the smoothest path forward would be, as @HsiangKai suggests, to only support VLEN>=64 and revisit 32. Supporting 32 is (I think) a much larger thing owing to our codegen assumptions on `VLEN` and `ELEN`. And, as @craig.topper said, there are a few little things that would probably be best prepared before this patch, replacing some of the calls to `hasStdExtV` at least (`hasVVectors`, for codegen purposes?). It sounds like we're unsure on some of the finer details about how the extensions interact.

I think our mapping from lmul/sew to <vscale x Y x iZ> types also break with VLEN=32. I haven't been able to figure out a single mapping that works for VLEN=32 and VLEN=64 and supports i64 vectors. To support VLEN=32 we need to reduce RVVBitsPerBlock to 32, but then you can't fit an i64 element into it.


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