[PATCH] D107790: [RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 369470.
craig.topper added a comment.

Move isLegalElementTypeForRVV from RISCVTargetTransformInfo to RISCVISelLowering to share it.

The TargetTransformInfoWrapperPass only gives access to a generic TargetTransformInfo
pointer. While I could cast that to RISCVTargetTransformInfo, I didn't see any
other targets doing that. So instead I just moved the function to ISelLowering
which can be accessed by this pass and by RISCVTargetTransformInfo.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107790/new/

https://reviews.llvm.org/D107790

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/CMakeLists.txt
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-negative.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
  llvm/tools/opt/opt.cpp

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