[PATCH] D108914: [X86] Copy X86SchedSkylakeServer.td to X86SchedIcelake.td

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: pengfei, craig.topper, lebedev.ri, courbet.
Herald added subscribers: mstojanovic, jfb, hiraditya.
RKSimon requested review of this revision.
Herald added a project: LLVM.

Icelake, Rocketlake and Tigerlake targets currently use the SkylakeServer scheduler model, despite being a later microarchitecture, leading to both reported bugs (PR48110) and discrepancies when comparing llvm-mca reports to other profiling tools (OSACA, uops, uica, etc.). And tbh I'm getting sick of llvm-mca getting blamed for what are backend scheduler model issues :-(

This patch doesn't attempt to fix any of these discrepancies - there should be no changes in codegen - its a setup patch that copies the skx model, renames all the resources, adds the additional ports (but doesn't reference them yet) and updates the llvm-exegesis pfm counter mappings (based off https://sourceforge.net/p/perfmon2/libpfm4/ci/master/tree/lib/events/intel_icl_events.h).

This should make it trivial for anyone with hardware access to use llvm-exegesis reports to iteratively improve the model (my attempts to get hold of a cheap tiger lake box haven't been fruitful yet....).

I haven't included any llvm-mca resource tests, but they are trivial to add once this patch is in place, but I can pre-commit the existing skylake tests if people think its useful (the diff should entirely be the resource renames).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108914

Files:
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86PfmCounters.td
  llvm/lib/Target/X86/X86SchedIcelake.td

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D108914.369429.patch
Type: text/x-patch
Size: 123509 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210830/cff9172d/attachment.bin>