[PATCH] D108902: [PowerPC] Enable track-subreg-liveness by default

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf created this revision.
qiucf added reviewers: PowerPC, nemanjai, jsji, shchenz, lkail, stefanp.
Herald added subscribers: kbarton, hiraditya, qcolombet, MatzeB.
qiucf requested review of this revision.
Herald added a project: LLVM.
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Enabling this option helps some MMA related cases to reduce unnecessary copies.

For `ppc64-acc-regalloc-bugfix.ll`, enabling this option causes failure. D108691 <https://reviews.llvm.org/D108691> tries to fix it.

For `pr45709.ll`, the function has attribute `optnone, the extra dead `lfs` was not moved to the bottom block. Dead machine instruction eliminator removes it when `optnone` disabled.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108902

Files:
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
  llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
  llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
  llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
  llvm/test/CodeGen/PowerPC/p10-spill-creq.ll
  llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll
  llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll
  llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
  llvm/test/CodeGen/PowerPC/ppc-fpclass.ll
  llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
  llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
  llvm/test/CodeGen/PowerPC/pr45709.ll
  llvm/test/CodeGen/PowerPC/spe.ll
  llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll

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