[PATCH] D108691: [PowerPC] Propagate undef from MMA assemble

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll:4
 ; RUN:     -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
-; RUN:    | FileCheck %s
+; RUN:     -ppc-track-subreg-liveness | FileCheck %s
 
----------------
lkail wrote:
> I don't quite understand you both add a new option and change the IR. The IR is legal and if adding this new option leads to a crash, I think we should seek the reason behind it. Changing IR might be a workaround, but not addressing the root cause.
I manually skipped removing `xxmtacc-xxmfacc` in pre-emit peephole, which satisfies machine verifier.

```
bb.0.dmblvi_entry:
  renamable $vsl3 = XXLXORz
  renamable $vsl0 = XXLXORz
  renamable $acc0 = XXMTACC killed renamable $acc0(tied-def 0)
  renamable $acc0 = XXMFACC killed renamable $acc0(tied-def 0)
  STXV killed renamable $vsl1, 0, $zero8 :: (store (s128) into `<16 x i8>* null`, align 1)
```

Here `stxv` is not error because `acc0` is partially defined. Is that an expected state?

Anyway, here `vsl1` is undefined, so it should be removed as if it's `stxv undef, ...` if we can track its state.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108691/new/

https://reviews.llvm.org/D108691