[PATCH] D107210: [RISCV] Support interleaved load lowering

[Luke via Phabricator via llvm-commits]

luke957 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1059
+
+    if(!isScalableVector){
+      Type *IntrinsicTypes[] = {cast<FixedVectorType>(VTy),
----------------
craig.topper wrote:
> Please address these clang-format warnings
Fix format.


================
Comment at: llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll:5
+
+define void @load_factor2(<16 x i8>* %ptr) {
+; CHECK-LABEL: @load_factor2(
----------------
craig.topper wrote:
> Why are we only testing one factor?
Add test case for factor 3 and 4.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107210/new/

https://reviews.llvm.org/D107210