[PATCH] D108793: Teach the AArch64 backend patterns to generate the EOR3 instruction.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sat Aug 28 12:42:02 PDT 2021


craig.topper added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:974
+class EOR3_pattern<ValueType VecTy>
+  : Pat<(xor (xor (VecTy V128:$Vn), (VecTy V128:$Vm)), (VecTy V128:$Va)),
+        (EOR3 (VecTy V128:$Vn), (VecTy V128:$Vm), (VecTy V128:$Va))>;
----------------
dmgreen wrote:
> resistor wrote:
> > craig.topper wrote:
> > > I don't the AArch64 ISA, but is it possible one of the xors is a vnot. And if that is possible, is EOR3 what you want to generate or would you want XOR+NOT?
> > This still behaves correctly with this patch. XOR + VNOT generates EOR + MVN.
> Sounds like it is worth adding some quick tests.
Looks like the ImmAllOnesV in the vnot weights as a build_vector plus plus an immediate. Because of that the vnot pattern has complexity 7 and the eor3 pattern has complexity 6.  So the vnot gets priority.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108793/new/

https://reviews.llvm.org/D108793



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