[PATCH] D108854: [AArch64][GlobalISel] Add a frame-index CSE optimization during post-select.

[Amara Emerson via Phabricator via llvm-commits]

aemerson created this revision.
aemerson added reviewers: paquette, qcolombet, arsenm, jroelofs.
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Herald added subscribers: arphaman, hiraditya, kristof.beyls, rovka.
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Frame index operands are replaced by physical registers during frame
lowering. Doing so however may require multiple instructions to be
generated in order to materialize the right stack pointer offset. In some
cases, like G_MEMCPY expansion, we might have many memory operations using
a frame index + offset addressing mode. If the object being referenced is
too far from the stack pointer, we could have multiple stack address
instructions generated for each memory operation.

This optimization tries to mitigate this problem by searching for
essentially CSE'ing away frame index operands within a block and replacing
the uses with the vreg of the frame index. It's gated on having a large
enough stack size to be likely to save materialization costs
(empirically landed on 2K bytes using CTMark -Os) and having enough uses
in a block to be worth a significant amount of savings if it does fire.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108854

Files:
  llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-frameidxcse.mir

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