[PATCH] D108815: [AMDGPU] Introduce RC flags for vector register classes

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:312
 
-def SCC_CLASS : RegisterClass<"AMDGPU", [i1], 1, (add SCC)> {
+def SCC_CLASS : SIRegisterClass<"AMDGPU", [i1], 1, (add SCC)> {
   let CopyCost = -1;
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rampitec wrote:
> Aren't TSFlags initialized to 0 by default? I think you can drop most of the changes to use SIRegisterClass and only keep it for VGPRs and AGPRs.
Yes, the bit vector is initialized to zero at its declaration statement in Target.td.

I thought having SIRegisterClass everywhere would make it simpler for any additional flags set in the future.
I could otherwise leave a comment where I define SIRegisterClass to indicate it and currently use it only for vector RCs.


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  https://reviews.llvm.org/D108815/new/

https://reviews.llvm.org/D108815