[PATCH] D108842: [ARMISelLowering] avoid emitting libcalls to __mulodi4()

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll:241
+entry:
+  %a.addr = alloca i32, align 4
+  %b.addr = alloca i64, align 8
----------------
nickdesaulniers wrote:
> craig.topper wrote:
> > Can you run this through mem2reg?
> If I do, then the test is no longer red before this change. Perhaps there is some other way to make this test less brittle?
> If I do, then the test is no longer red before this change. Perhaps there is some other way to make this test less brittle?

That's weird it seems to work for me. I just wanted to get rid of the allocas and associate load/stores

```
define void @no__mulodi4(i32 %a, i64 %b, i32* %c) {
entry:
  %0 = sext i32 %a to i64
  %1 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %0, i64 %b)
  %2 = extractvalue { i64, i1 } %1, 1
  %3 = extractvalue { i64, i1 } %1, 0
  %4 = trunc i64 %3 to i32
  %5 = sext i32 %4 to i64
  %6 = icmp ne i64 %3, %5
  %7 = or i1 %2, %6
  store i32 %4, i32* %c, align 4
  ret void
}
```

This should be even better since it prevents %10 from being dead code

```
define zeroext i1 @no__mulodi4(i32 %a, i64 %b, i32* %c) {
entry:
  %0 = sext i32 %a to i64
  %1 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %0, i64 %b)
  %2 = extractvalue { i64, i1 } %1, 1
  %3 = extractvalue { i64, i1 } %1, 0
  %4 = trunc i64 %3 to i32
  %5 = sext i32 %4 to i64
  %6 = icmp ne i64 %3, %5
  %7 = or i1 %2, %6
  store i32 %4, i32* %c, align 4
  ret i1 %7
}
```


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D108842/new/

https://reviews.llvm.org/D108842