[PATCH] D108793: Teach the AArch64 backend patterns to generate the EOR3 instruction.

[Owen Anderson via Phabricator via llvm-commits]

resistor added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:974
+class EOR3_pattern<ValueType VecTy>
+  : Pat<(xor (xor (VecTy V128:$Vn), (VecTy V128:$Vm)), (VecTy V128:$Va)),
+        (EOR3 (VecTy V128:$Vn), (VecTy V128:$Vm), (VecTy V128:$Va))>;
----------------
craig.topper wrote:
> I don't the AArch64 ISA, but is it possible one of the xors is a vnot. And if that is possible, is EOR3 what you want to generate or would you want XOR+NOT?
This still behaves correctly with this patch. XOR + VNOT generates EOR + MVN.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108793/new/

https://reviews.llvm.org/D108793