[PATCH] D108842: [ARMISelLowering] avoid emitting libcalls to __mulodi4()

[Nick Desaulniers via Phabricator via llvm-commits]

nickdesaulniers created this revision.
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__has_builtin(__builtin_mul_overflow) return true for 32b ARM targets,
but Clang is deferring to compiler RT when encountering `long long`
types. This breaks sanitizer builds of the Linux kernel that are using
__builtin_mul_overflow with these types for these targets.

If the semantics of __has_builtin mean "the compiler resolves these,
always" then we shouldn't conditionally emit a libcall.

This will still need to be worked around in the Linux kernel in order to
continue to support allmodconfig builds of the Linux kernel for this
target with older releases of clang.

Link: https://bugs.llvm.org/show_bug.cgi?id=28629
Link: https://github.com/ClangBuiltLinux/linux/issues/1438


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108842

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll


Index: llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll
===================================================================
--- llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll
+++ llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll
@@ -234,6 +234,31 @@
   ret i32 %conv
 }
 
+define void @no__mulodi4(i32 %a, i64 %b, i32* %c) {
+; CHECK-LABEL: no__mulodi4
+; CHECK-NOT: bl __mulodi4
+entry:
+  %a.addr = alloca i32, align 4
+  %b.addr = alloca i64, align 8
+  %c.addr = alloca i32*, align 4
+  store i32 %a, i32* %a.addr, align 4
+  store i64 %b, i64* %b.addr, align 8
+  store i32* %c, i32** %c.addr, align 4
+  %0 = load i32, i32* %a.addr, align 4
+  %1 = load i64, i64* %b.addr, align 8
+  %2 = load i32*, i32** %c.addr, align 4
+  %3 = sext i32 %0 to i64
+  %4 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %3, i64 %1)
+  %5 = extractvalue { i64, i1 } %4, 1
+  %6 = extractvalue { i64, i1 } %4, 0
+  %7 = trunc i64 %6 to i32
+  %8 = sext i32 %7 to i64
+  %9 = icmp ne i64 %6, %8
+  %10 = or i1 %5, %9
+  store i32 %7, i32* %2, align 4
+  ret void
+}
+
 declare void @llvm.trap() #2
 declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) #1
 declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) #1
@@ -241,3 +266,4 @@
 declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #1
 declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32) #1
 declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32) #1
+declare { i64, i1 } @llvm.smul.with.overflow.i64(i64, i64)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -545,6 +545,7 @@
   setLibcallName(RTLIB::SRL_I128, nullptr);
   setLibcallName(RTLIB::SRA_I128, nullptr);
   setLibcallName(RTLIB::MUL_I128, nullptr);
+  setLibcallName(RTLIB::MULO_I64, nullptr);
 
   // RTLIB
   if (Subtarget->isAAPCS_ABI() &&


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