[PATCH] D108793: Teach the AArch64 backend patterns to generate the EOR3 instruction.

Fri Aug 27 10:52:40 PDT 2021

resistor marked 3 inline comments as done.
resistor added inline comments.

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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:976
+        (EOR3 (VecTy V128:$Vn), (VecTy V128:$Vm), (VecTy V128:$Va))>;
+  def : Pat<(xor (VecTy V128:$Vn) (xor (VecTy V128:$Vm), (VecTy V128:$Va)),
+        (EOR3 (VecTy V128:$Vn), (VecTy V128:$Vm), (VecTy V128:$Va))>;
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dmgreen wrote:
> dmgreen wrote:
> > There's a comma missing here. The brackets also look off.
> Oh xor is also commutative. You likely don't need both the patterns, it will be handled automatically by tablegen.
> 
> Having tests that check that sound good to have though.
I do have tests for the different ways to commute it already. Good call that tblgen should handle the commutation automatically.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108793/new/

https://reviews.llvm.org/D108793