[PATCH] D108821: [Codegen][X86] EltsFromConsecutiveLoads(): if only have AVX1, ensure that the "load" is actually foldable (PR51615)

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri created this revision.
lebedev.ri added reviewers: spatel, RKSimon, craig.topper.
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This fixes another reproducer from https://bugs.llvm.org/show_bug.cgi?id=51615
And again, the fix lies not in the code added in D105390 <https://reviews.llvm.org/D105390>

In this case, we completely don't check that the "broadcast-from-mem" we create
can actually fold the load. In this case, it's operand was not a load at all:

  Optimized legalized selection DAG: %bb.3 'widget:bb17'
  SelectionDAG has 25 nodes:
    t0: ch = EntryToken
      t2: i64,ch = CopyFromReg t0, Register:i64 %0
    t40: v4i32,ch = load<(load (s128) from %ir.arg)> t0, t2, undef:i64
      t21: f32,ch = CopyFromReg t0, Register:f32 %3
    t43: i32 = X86ISD::FCMP t21, ConstantFP:f32<0.000000e+00>
              t36: i32 = extract_vector_elt t40, Constant:i64<0>
              t10: i64,ch = CopyFromReg t0, Register:i64 %1
            t11: ch = store<(store (s32) into %ir.arg12)> t40:1, t36, t10, undef:i64
            t37: v8i32 = X86ISD::VBROADCAST t40
            t18: i64,ch = CopyFromReg t0, Register:i64 %2
          t19: ch = store<(store (s256) into %ir.arg13)> t11, t37, t18, undef:i64
        t45: ch = X86ISD::BRCOND t19, BasicBlock:ch<bb17 0xd03798>, TargetConstant:i8<5>, t43
      t47: ch = X86ISD::BRCOND t45, BasicBlock:ch<bb17 0xd03798>, TargetConstant:i8<10>, t43
    t28: ch = br t47, BasicBlock:ch<bb16 0xd035d8>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108821

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/pr51615.ll

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