[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

[LuoYuanke via Phabricator via llvm-commits]

LuoYuanke added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:47419
+                                                       : X86ISD::VFCMADDC;
+  // FIXME: How we handle when FMF of FADD is different from CFMUL's?
+  CFmul = DAG.getNode(newOp, SDLoc(N), CVT, FAddOp1, CFmul.getOperand(0),
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RKSimon wrote:
> LuoYuanke wrote:
> > Sorry, I don't understand the comments. What does FMF mean?
> fast math flags?
I understand now. Thanks, Simon. :)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105269/new/

https://reviews.llvm.org/D105269