[PATCH] D108793: Teach the AArch64 backend patterns to generate the EOR3 instruction.

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

This doesn't look like it even parses correctly! Nice idea though, it sounds good to add patterns for these three way eor's. I'm surprised they weren't added when the intrinsics were added.



================
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:976
+        (EOR3 (VecTy V128:$Vn), (VecTy V128:$Vm), (VecTy V128:$Va))>;
+  def : Pat<(xor (VecTy V128:$Vn) (xor (VecTy V128:$Vm), (VecTy V128:$Va)),
+        (EOR3 (VecTy V128:$Vn), (VecTy V128:$Vm), (VecTy V128:$Va))>;
----------------
There's a comma missing here. The brackets also look off.


================
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:979
+}
+def : EOR3_pattern<v16i8>;
+def : EOR3_pattern<v8i16>;
----------------
defm?


================
Comment at: llvm/test/CodeGen/AArch64/eor3.ll:1
+; RUN: llc -march=aarch64 -mattr=+sha3 < %s | FileCheck %s
+
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-mtriple=aarch64-none-eabi?

This file can use update_llc_test_checks. Preferably for run lines with and without +sha3


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D108793/new/

https://reviews.llvm.org/D108793