[PATCH] D108706: [AArch64][SVE] Optimize ptrue predicate pattern with known sve register width.

[JunMa via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG15b2a8e7faf6: [AArch64][SVE] Optimize ptrue predicate pattern with known sve register width. (authored by junparser).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108706/new/

https://reviews.llvm.org/D108706

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
  llvm/test/CodeGen/AArch64/sve-extract-vector.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-optimize-ptrue.ll
  llvm/test/CodeGen/AArch64/sve-insert-vector.ll
  llvm/test/CodeGen/AArch64/sve-vscale-attr.ll

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