[PATCH] D108706: [AArch64][SVE] Optimize ptrue predicate pattern with known sve register width.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm accepted this revision.
paulwalker-arm added a comment.
This revision is now accepted and ready to land.

I know the patch triggers existing test changes but I'd prefer to have an explicit test for this functionality.  Noting complicated, perhaps just a 512bit vector add/fadd test for each element type. You can probably just copy them from `sve-fixed-length-{int,fp}-arith.ll` (i.e. add_v256i8, add_v128i16 ...) and let `update_llc_test_checks.py` do its stuff.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D108706/new/

https://reviews.llvm.org/D108706