[llvm] 46d82e7 - AMDGPU: Restrict attributor transforms
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 26 18:08:56 PDT 2021
Author: Matt Arsenault
Date: 2021-08-26T21:08:51-04:00
New Revision: 46d82e7357e7b1330b1f837c7d28e3821092ddd6
URL: https://github.com/llvm/llvm-project/commit/46d82e7357e7b1330b1f837c7d28e3821092ddd6
DIFF: https://github.com/llvm/llvm-project/commit/46d82e7357e7b1330b1f837c7d28e3821092ddd6.diff
LOG: AMDGPU: Restrict attributor transforms
We only really want this to add the custom attributes. Theoretically
the regular transforms were already run at this point. Touching
undefined behavior breaks a lot of tests when this is enabled by
default, many of which are expecting to test handling of undef
operations.
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll
llvm/test/CodeGen/AMDGPU/uniform-work-group-attribute-missing.ll
llvm/test/CodeGen/AMDGPU/uniform-work-group-multistep.ll
llvm/test/CodeGen/AMDGPU/uniform-work-group-nested-function-calls.ll
llvm/test/CodeGen/AMDGPU/uniform-work-group-prevent-attribute-propagation.ll
llvm/test/CodeGen/AMDGPU/uniform-work-group-propagate-attribute.ll
llvm/test/CodeGen/AMDGPU/uniform-work-group-recursion-test.ll
llvm/test/CodeGen/AMDGPU/uniform-work-group-test.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
index 9e4b65709659..f4746be4dfe3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
@@ -481,7 +481,10 @@ class AMDGPUAttributor : public ModulePass {
CallGraphUpdater CGUpdater;
BumpPtrAllocator Allocator;
AMDGPUInformationCache InfoCache(M, AG, Allocator, nullptr, *TM);
- Attributor A(Functions, InfoCache, CGUpdater);
+ DenseSet<const char *> Allowed(
+ {&AAAMDAttributes::ID, &AAAMDWorkGroupSize::ID, &AACallEdges::ID});
+
+ Attributor A(Functions, InfoCache, CGUpdater, &Allowed);
for (Function &F : M) {
if (!F.isIntrinsic()) {
diff --git a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
index 3ebe08381259..fbe05e399a61 100644
--- a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
@@ -27,7 +27,8 @@ define void @use_workitem_id_x() #1 {
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_workitem_id_x
; ATTRIBUTOR_HSA-SAME: () #[[ATTR1:[0-9]+]] {
-; ATTRIBUTOR_HSA-NEXT: store volatile i32 undef, i32 addrspace(1)* undef, align 4
+; ATTRIBUTOR_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
+; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL]], i32 addrspace(1)* undef, align 4
; ATTRIBUTOR_HSA-NEXT: ret void
;
%val = call i32 @llvm.amdgcn.workitem.id.x()
@@ -43,8 +44,9 @@ define void @use_workitem_id_y() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_workitem_id_y
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: store volatile i32 undef, i32 addrspace(1)* undef, align 4
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR2:[0-9]+]] {
+; ATTRIBUTOR_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
+; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL]], i32 addrspace(1)* undef, align 4
; ATTRIBUTOR_HSA-NEXT: ret void
;
%val = call i32 @llvm.amdgcn.workitem.id.y()
@@ -60,8 +62,9 @@ define void @use_workitem_id_z() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_workitem_id_z
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: store volatile i32 undef, i32 addrspace(1)* undef, align 4
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR3:[0-9]+]] {
+; ATTRIBUTOR_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()
+; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL]], i32 addrspace(1)* undef, align 4
; ATTRIBUTOR_HSA-NEXT: ret void
;
%val = call i32 @llvm.amdgcn.workitem.id.z()
@@ -77,8 +80,9 @@ define void @use_workgroup_id_x() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_workgroup_id_x
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: store volatile i32 undef, i32 addrspace(1)* undef, align 4
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR4:[0-9]+]] {
+; ATTRIBUTOR_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x()
+; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL]], i32 addrspace(1)* undef, align 4
; ATTRIBUTOR_HSA-NEXT: ret void
;
%val = call i32 @llvm.amdgcn.workgroup.id.x()
@@ -94,8 +98,9 @@ define void @use_workgroup_id_y() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_workgroup_id_y
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: store volatile i32 undef, i32 addrspace(1)* undef, align 4
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR5:[0-9]+]] {
+; ATTRIBUTOR_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y()
+; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL]], i32 addrspace(1)* undef, align 4
; ATTRIBUTOR_HSA-NEXT: ret void
;
%val = call i32 @llvm.amdgcn.workgroup.id.y()
@@ -111,8 +116,9 @@ define void @use_workgroup_id_z() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_workgroup_id_z
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: store volatile i32 undef, i32 addrspace(1)* undef, align 4
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR6:[0-9]+]] {
+; ATTRIBUTOR_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z()
+; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL]], i32 addrspace(1)* undef, align 4
; ATTRIBUTOR_HSA-NEXT: ret void
;
%val = call i32 @llvm.amdgcn.workgroup.id.z()
@@ -128,8 +134,9 @@ define void @use_dispatch_ptr() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_dispatch_ptr
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: store volatile i8 addrspace(4)* undef, i8 addrspace(4)* addrspace(1)* undef, align 8
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR7:[0-9]+]] {
+; ATTRIBUTOR_HSA-NEXT: [[DISPATCH_PTR:%.*]] = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
+; ATTRIBUTOR_HSA-NEXT: store volatile i8 addrspace(4)* [[DISPATCH_PTR]], i8 addrspace(4)* addrspace(1)* undef, align 8
; ATTRIBUTOR_HSA-NEXT: ret void
;
%dispatch.ptr = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
@@ -145,8 +152,9 @@ define void @use_queue_ptr() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_queue_ptr
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: store volatile i8 addrspace(4)* undef, i8 addrspace(4)* addrspace(1)* undef, align 8
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR8:[0-9]+]] {
+; ATTRIBUTOR_HSA-NEXT: [[QUEUE_PTR:%.*]] = call i8 addrspace(4)* @llvm.amdgcn.queue.ptr()
+; ATTRIBUTOR_HSA-NEXT: store volatile i8 addrspace(4)* [[QUEUE_PTR]], i8 addrspace(4)* addrspace(1)* undef, align 8
; ATTRIBUTOR_HSA-NEXT: ret void
;
%queue.ptr = call i8 addrspace(4)* @llvm.amdgcn.queue.ptr()
@@ -162,8 +170,9 @@ define void @use_dispatch_id() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_dispatch_id
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: store volatile i64 undef, i64 addrspace(1)* undef, align 4
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR9:[0-9]+]] {
+; ATTRIBUTOR_HSA-NEXT: [[VAL:%.*]] = call i64 @llvm.amdgcn.dispatch.id()
+; ATTRIBUTOR_HSA-NEXT: store volatile i64 [[VAL]], i64 addrspace(1)* undef, align 4
; ATTRIBUTOR_HSA-NEXT: ret void
;
%val = call i64 @llvm.amdgcn.dispatch.id()
@@ -181,9 +190,11 @@ define void @use_workgroup_id_y_workgroup_id_z() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_workgroup_id_y_workgroup_id_z
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: store volatile i32 undef, i32 addrspace(1)* undef, align 4
-; ATTRIBUTOR_HSA-NEXT: store volatile i32 undef, i32 addrspace(1)* undef, align 4
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR10:[0-9]+]] {
+; ATTRIBUTOR_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y()
+; ATTRIBUTOR_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z()
+; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL0]], i32 addrspace(1)* undef, align 4
+; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL1]], i32 addrspace(1)* undef, align 4
; ATTRIBUTOR_HSA-NEXT: ret void
;
%val0 = call i32 @llvm.amdgcn.workgroup.id.y()
@@ -201,7 +212,7 @@ define void @func_indirect_use_workitem_id_x() #1 {
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_indirect_use_workitem_id_x
; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: call void @use_workitem_id_x() #[[ATTR9:[0-9]+]]
+; ATTRIBUTOR_HSA-NEXT: call void @use_workitem_id_x()
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @use_workitem_id_x()
@@ -216,7 +227,7 @@ define void @kernel_indirect_use_workitem_id_x() #1 {
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@kernel_indirect_use_workitem_id_x
; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: call void @use_workitem_id_x() #[[ATTR9]]
+; ATTRIBUTOR_HSA-NEXT: call void @use_workitem_id_x()
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @use_workitem_id_x()
@@ -230,8 +241,8 @@ define void @func_indirect_use_workitem_id_y() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_indirect_use_workitem_id_y
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: call void @use_workitem_id_y() #[[ATTR9]]
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR2]] {
+; ATTRIBUTOR_HSA-NEXT: call void @use_workitem_id_y()
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @use_workitem_id_y()
@@ -245,8 +256,8 @@ define void @func_indirect_use_workitem_id_z() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_indirect_use_workitem_id_z
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: call void @use_workitem_id_z() #[[ATTR9]]
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR3]] {
+; ATTRIBUTOR_HSA-NEXT: call void @use_workitem_id_z()
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @use_workitem_id_z()
@@ -260,8 +271,8 @@ define void @func_indirect_use_workgroup_id_x() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_indirect_use_workgroup_id_x
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: call void @use_workgroup_id_x() #[[ATTR9]]
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR4]] {
+; ATTRIBUTOR_HSA-NEXT: call void @use_workgroup_id_x()
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @use_workgroup_id_x()
@@ -275,8 +286,8 @@ define void @kernel_indirect_use_workgroup_id_x() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@kernel_indirect_use_workgroup_id_x
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: call void @use_workgroup_id_x() #[[ATTR9]]
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR4]] {
+; ATTRIBUTOR_HSA-NEXT: call void @use_workgroup_id_x()
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @use_workgroup_id_x()
@@ -290,8 +301,8 @@ define void @func_indirect_use_workgroup_id_y() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_indirect_use_workgroup_id_y
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: call void @use_workgroup_id_y() #[[ATTR9]]
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR5]] {
+; ATTRIBUTOR_HSA-NEXT: call void @use_workgroup_id_y()
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @use_workgroup_id_y()
@@ -305,8 +316,8 @@ define void @func_indirect_use_workgroup_id_z() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_indirect_use_workgroup_id_z
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: call void @use_workgroup_id_z() #[[ATTR9]]
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR6]] {
+; ATTRIBUTOR_HSA-NEXT: call void @use_workgroup_id_z()
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @use_workgroup_id_z()
@@ -320,8 +331,8 @@ define void @func_indirect_indirect_use_workgroup_id_y() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_indirect_indirect_use_workgroup_id_y
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: call void @func_indirect_use_workgroup_id_y() #[[ATTR9]]
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR5]] {
+; ATTRIBUTOR_HSA-NEXT: call void @func_indirect_use_workgroup_id_y()
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @func_indirect_use_workgroup_id_y()
@@ -335,8 +346,8 @@ define void @indirect_x2_use_workgroup_id_y() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@indirect_x2_use_workgroup_id_y
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: call void @func_indirect_indirect_use_workgroup_id_y() #[[ATTR9]]
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR5]] {
+; ATTRIBUTOR_HSA-NEXT: call void @func_indirect_indirect_use_workgroup_id_y()
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @func_indirect_indirect_use_workgroup_id_y()
@@ -350,8 +361,8 @@ define void @func_indirect_use_dispatch_ptr() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_indirect_use_dispatch_ptr
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: call void @use_dispatch_ptr() #[[ATTR9]]
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR7]] {
+; ATTRIBUTOR_HSA-NEXT: call void @use_dispatch_ptr()
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @use_dispatch_ptr()
@@ -365,8 +376,8 @@ define void @func_indirect_use_queue_ptr() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_indirect_use_queue_ptr
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: call void @use_queue_ptr() #[[ATTR9]]
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR8]] {
+; ATTRIBUTOR_HSA-NEXT: call void @use_queue_ptr()
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @use_queue_ptr()
@@ -380,8 +391,8 @@ define void @func_indirect_use_dispatch_id() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_indirect_use_dispatch_id
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: call void @use_dispatch_id() #[[ATTR9]]
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR9]] {
+; ATTRIBUTOR_HSA-NEXT: call void @use_dispatch_id()
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @use_dispatch_id()
@@ -395,8 +406,9 @@ define void @func_indirect_use_workgroup_id_y_workgroup_id_z() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_indirect_use_workgroup_id_y_workgroup_id_z
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR2:[0-9]+]] {
-; ATTRIBUTOR_HSA-NEXT: unreachable
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR11:[0-9]+]] {
+; ATTRIBUTOR_HSA-NEXT: call void @func_indirect_use_workgroup_id_y_workgroup_id_z()
+; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @func_indirect_use_workgroup_id_y_workgroup_id_z()
ret void
@@ -411,10 +423,11 @@ define void @recursive_use_workitem_id_y() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@recursive_use_workitem_id_y
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR3:[0-9]+]] {
-; ATTRIBUTOR_HSA-NEXT: store volatile i32 undef, i32 addrspace(1)* undef, align 4
-; ATTRIBUTOR_HSA-NEXT: call void @recursive_use_workitem_id_y() #[[ATTR10:[0-9]+]]
-; ATTRIBUTOR_HSA-NEXT: unreachable
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR2]] {
+; ATTRIBUTOR_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
+; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL]], i32 addrspace(1)* undef, align 4
+; ATTRIBUTOR_HSA-NEXT: call void @recursive_use_workitem_id_y()
+; ATTRIBUTOR_HSA-NEXT: ret void
;
%val = call i32 @llvm.amdgcn.workitem.id.y()
store volatile i32 %val, i32 addrspace(1)* undef
@@ -429,9 +442,9 @@ define void @call_recursive_use_workitem_id_y() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@call_recursive_use_workitem_id_y
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: call void @recursive_use_workitem_id_y() #[[ATTR10]]
-; ATTRIBUTOR_HSA-NEXT: unreachable
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR2]] {
+; ATTRIBUTOR_HSA-NEXT: call void @recursive_use_workitem_id_y()
+; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @recursive_use_workitem_id_y()
ret void
@@ -445,7 +458,7 @@ define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_group_to_flat_addrspacecast
-; ATTRIBUTOR_HSA-SAME: (i32 addrspace(3)* [[PTR:%.*]]) #[[ATTR4:[0-9]+]] {
+; ATTRIBUTOR_HSA-SAME: (i32 addrspace(3)* [[PTR:%.*]]) #[[ATTR8]] {
; ATTRIBUTOR_HSA-NEXT: [[STOF:%.*]] = addrspacecast i32 addrspace(3)* [[PTR]] to i32 addrspace(4)*
; ATTRIBUTOR_HSA-NEXT: store volatile i32 0, i32 addrspace(4)* [[STOF]], align 4
; ATTRIBUTOR_HSA-NEXT: ret void
@@ -464,7 +477,7 @@ define void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* %ptr) #2 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_group_to_flat_addrspacecast_gfx9
-; ATTRIBUTOR_HSA-SAME: (i32 addrspace(3)* [[PTR:%.*]]) #[[ATTR5:[0-9]+]] {
+; ATTRIBUTOR_HSA-SAME: (i32 addrspace(3)* [[PTR:%.*]]) #[[ATTR12:[0-9]+]] {
; ATTRIBUTOR_HSA-NEXT: [[STOF:%.*]] = addrspacecast i32 addrspace(3)* [[PTR]] to i32 addrspace(4)*
; ATTRIBUTOR_HSA-NEXT: store volatile i32 0, i32 addrspace(4)* [[STOF]], align 4
; ATTRIBUTOR_HSA-NEXT: ret void
@@ -483,10 +496,10 @@ define void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* %p
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_group_to_flat_addrspacecast_queue_ptr_gfx9
-; ATTRIBUTOR_HSA-SAME: (i32 addrspace(3)* [[PTR:%.*]]) #[[ATTR5]] {
+; ATTRIBUTOR_HSA-SAME: (i32 addrspace(3)* [[PTR:%.*]]) #[[ATTR13:[0-9]+]] {
; ATTRIBUTOR_HSA-NEXT: [[STOF:%.*]] = addrspacecast i32 addrspace(3)* [[PTR]] to i32 addrspace(4)*
; ATTRIBUTOR_HSA-NEXT: store volatile i32 0, i32 addrspace(4)* [[STOF]], align 4
-; ATTRIBUTOR_HSA-NEXT: call void @func_indirect_use_queue_ptr() #[[ATTR9]]
+; ATTRIBUTOR_HSA-NEXT: call void @func_indirect_use_queue_ptr()
; ATTRIBUTOR_HSA-NEXT: ret void
;
%stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)*
@@ -502,8 +515,8 @@ define void @indirect_use_group_to_flat_addrspacecast() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@indirect_use_group_to_flat_addrspacecast
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR4]] {
-; ATTRIBUTOR_HSA-NEXT: call void @use_group_to_flat_addrspacecast(i32 addrspace(3)* null) #[[ATTR9]]
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR8]] {
+; ATTRIBUTOR_HSA-NEXT: call void @use_group_to_flat_addrspacecast(i32 addrspace(3)* null)
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @use_group_to_flat_addrspacecast(i32 addrspace(3)* null)
@@ -517,8 +530,8 @@ define void @indirect_use_group_to_flat_addrspacecast_gfx9() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@indirect_use_group_to_flat_addrspacecast_gfx9
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: call void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* null) #[[ATTR9]]
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR11]] {
+; ATTRIBUTOR_HSA-NEXT: call void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* null)
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* null)
@@ -532,8 +545,8 @@ define void @indirect_use_group_to_flat_addrspacecast_queue_ptr_gfx9() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@indirect_use_group_to_flat_addrspacecast_queue_ptr_gfx9
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: call void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* null) #[[ATTR9]]
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR8]] {
+; ATTRIBUTOR_HSA-NEXT: call void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* null)
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* null)
@@ -548,8 +561,9 @@ define void @use_kernarg_segment_ptr() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_kernarg_segment_ptr
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: store volatile i8 addrspace(4)* undef, i8 addrspace(4)* addrspace(1)* undef, align 8
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR11]] {
+; ATTRIBUTOR_HSA-NEXT: [[KERNARG_SEGMENT_PTR:%.*]] = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
+; ATTRIBUTOR_HSA-NEXT: store volatile i8 addrspace(4)* [[KERNARG_SEGMENT_PTR]], i8 addrspace(4)* addrspace(1)* undef, align 8
; ATTRIBUTOR_HSA-NEXT: ret void
;
%kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
@@ -563,8 +577,8 @@ define void @func_indirect_use_kernarg_segment_ptr() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_indirect_use_kernarg_segment_ptr
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: call void @use_kernarg_segment_ptr() #[[ATTR9]]
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR11]] {
+; ATTRIBUTOR_HSA-NEXT: call void @use_kernarg_segment_ptr()
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @use_kernarg_segment_ptr()
@@ -579,8 +593,9 @@ define amdgpu_kernel void @kern_use_implicitarg_ptr() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@kern_use_implicitarg_ptr
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: store volatile i8 addrspace(4)* undef, i8 addrspace(4)* addrspace(1)* undef, align 8
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR14:[0-9]+]] {
+; ATTRIBUTOR_HSA-NEXT: [[IMPLICITARG_PTR:%.*]] = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
+; ATTRIBUTOR_HSA-NEXT: store volatile i8 addrspace(4)* [[IMPLICITARG_PTR]], i8 addrspace(4)* addrspace(1)* undef, align 8
; ATTRIBUTOR_HSA-NEXT: ret void
;
%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
@@ -596,8 +611,9 @@ define void @use_implicitarg_ptr() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_implicitarg_ptr
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: store volatile i8 addrspace(4)* undef, i8 addrspace(4)* addrspace(1)* undef, align 8
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR14]] {
+; ATTRIBUTOR_HSA-NEXT: [[IMPLICITARG_PTR:%.*]] = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
+; ATTRIBUTOR_HSA-NEXT: store volatile i8 addrspace(4)* [[IMPLICITARG_PTR]], i8 addrspace(4)* addrspace(1)* undef, align 8
; ATTRIBUTOR_HSA-NEXT: ret void
;
%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
@@ -612,8 +628,8 @@ define void @func_indirect_use_implicitarg_ptr() #1 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_indirect_use_implicitarg_ptr
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: call void @use_implicitarg_ptr() #[[ATTR9]]
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR14]] {
+; ATTRIBUTOR_HSA-NEXT: call void @use_implicitarg_ptr()
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @use_implicitarg_ptr()
@@ -627,6 +643,10 @@ define internal void @defined.func() #3 {
; AKF_HSA-LABEL: define {{[^@]+}}@defined.func
; AKF_HSA-SAME: () #[[ATTR16:[0-9]+]] {
; AKF_HSA-NEXT: ret void
+;
+; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@defined.func
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR16:[0-9]+]] {
+; ATTRIBUTOR_HSA-NEXT: ret void
;
ret void
}
@@ -638,8 +658,8 @@ define void @func_call_external() #3 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_call_external
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR6:[0-9]+]] {
-; ATTRIBUTOR_HSA-NEXT: call void @external.func() #[[ATTR9]]
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR15:[0-9]+]] {
+; ATTRIBUTOR_HSA-NEXT: call void @external.func()
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @external.func()
@@ -653,7 +673,8 @@ define void @func_call_defined() #3 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_call_defined
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR7:[0-9]+]] {
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR16]] {
+; ATTRIBUTOR_HSA-NEXT: call void @defined.func()
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @defined.func()
@@ -666,8 +687,8 @@ define void @func_call_asm() #3 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_call_asm
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR7]] {
-; ATTRIBUTOR_HSA-NEXT: call void asm sideeffect "", ""() #[[ATTR9]]
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR16]] {
+; ATTRIBUTOR_HSA-NEXT: call void asm sideeffect "", ""() #[[ATTR18:[0-9]+]]
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void asm sideeffect "", ""() #3
@@ -681,8 +702,8 @@ define amdgpu_kernel void @kern_call_external() #3 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@kern_call_external
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR6]] {
-; ATTRIBUTOR_HSA-NEXT: call void @external.func() #[[ATTR9]]
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR15]] {
+; ATTRIBUTOR_HSA-NEXT: call void @external.func()
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @external.func()
@@ -696,7 +717,8 @@ define amdgpu_kernel void @func_kern_defined() #3 {
; AKF_HSA-NEXT: ret void
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_kern_defined
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR7]] {
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR16]] {
+; ATTRIBUTOR_HSA-NEXT: call void @defined.func()
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void @defined.func()
@@ -711,8 +733,9 @@ define i32 @use_dispatch_ptr_ret_type() #1 {
; AKF_HSA-NEXT: ret i32 0
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_dispatch_ptr_ret_type
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR8:[0-9]+]] {
-; ATTRIBUTOR_HSA-NEXT: store volatile i8 addrspace(4)* undef, i8 addrspace(4)* addrspace(1)* undef, align 8
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR17:[0-9]+]] {
+; ATTRIBUTOR_HSA-NEXT: [[DISPATCH_PTR:%.*]] = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
+; ATTRIBUTOR_HSA-NEXT: store volatile i8 addrspace(4)* [[DISPATCH_PTR]], i8 addrspace(4)* addrspace(1)* undef, align 8
; ATTRIBUTOR_HSA-NEXT: ret i32 0
;
%dispatch.ptr = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
@@ -728,7 +751,7 @@ define float @func_indirect_use_dispatch_ptr_constexpr_cast_func() #1 {
; AKF_HSA-NEXT: ret float [[FADD]]
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_indirect_use_dispatch_ptr_constexpr_cast_func
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR8]] {
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR17]] {
; ATTRIBUTOR_HSA-NEXT: [[F:%.*]] = call float bitcast (i32 ()* @use_dispatch_ptr_ret_type to float ()*)()
; ATTRIBUTOR_HSA-NEXT: [[FADD:%.*]] = fadd float [[F]], 1.000000e+00
; ATTRIBUTOR_HSA-NEXT: ret float [[FADD]]
@@ -746,7 +769,7 @@ define float @func_indirect_call(float()* %fptr) #3 {
; AKF_HSA-NEXT: ret float [[FADD]]
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_indirect_call
-; ATTRIBUTOR_HSA-SAME: (float ()* [[FPTR:%.*]]) #[[ATTR6]] {
+; ATTRIBUTOR_HSA-SAME: (float ()* [[FPTR:%.*]]) #[[ATTR15]] {
; ATTRIBUTOR_HSA-NEXT: [[F:%.*]] = call float [[FPTR]]()
; ATTRIBUTOR_HSA-NEXT: [[FADD:%.*]] = fadd float [[F]], 1.000000e+00
; ATTRIBUTOR_HSA-NEXT: ret float [[FADD]]
@@ -765,8 +788,8 @@ define float @func_extern_call() #3 {
; AKF_HSA-NEXT: ret float [[FADD]]
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_extern_call
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR6]] {
-; ATTRIBUTOR_HSA-NEXT: [[F:%.*]] = call float @extern() #[[ATTR9]]
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR15]] {
+; ATTRIBUTOR_HSA-NEXT: [[F:%.*]] = call float @extern()
; ATTRIBUTOR_HSA-NEXT: [[FADD:%.*]] = fadd float [[F]], 1.000000e+00
; ATTRIBUTOR_HSA-NEXT: ret float [[FADD]]
;
@@ -783,7 +806,7 @@ define float @func_null_call(float()* %fptr) #3 {
; AKF_HSA-NEXT: ret float [[FADD]]
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_null_call
-; ATTRIBUTOR_HSA-SAME: (float ()* [[FPTR:%.*]]) #[[ATTR6]] {
+; ATTRIBUTOR_HSA-SAME: (float ()* [[FPTR:%.*]]) #[[ATTR15]] {
; ATTRIBUTOR_HSA-NEXT: [[F:%.*]] = call float null()
; ATTRIBUTOR_HSA-NEXT: [[FADD:%.*]] = fadd float [[F]], 1.000000e+00
; ATTRIBUTOR_HSA-NEXT: ret float [[FADD]]
@@ -804,7 +827,7 @@ define float @func_other_intrinsic_call(float %arg) #3 {
; AKF_HSA-NEXT: ret float [[FADD]]
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_other_intrinsic_call
-; ATTRIBUTOR_HSA-SAME: (float [[ARG:%.*]]) #[[ATTR7]] {
+; ATTRIBUTOR_HSA-SAME: (float [[ARG:%.*]]) #[[ATTR16]] {
; ATTRIBUTOR_HSA-NEXT: [[F:%.*]] = call float @llvm.amdgcn.rcp.f32(float [[ARG]])
; ATTRIBUTOR_HSA-NEXT: [[FADD:%.*]] = fadd float [[F]], 1.000000e+00
; ATTRIBUTOR_HSA-NEXT: ret float [[FADD]]
@@ -843,14 +866,22 @@ attributes #3 = { nounwind }
; AKF_HSA: attributes #[[ATTR20]] = { nounwind "amdgpu-dispatch-id" "amdgpu-dispatch-ptr" "amdgpu-implicitarg-ptr" "amdgpu-queue-ptr" "amdgpu-work-group-id-x" "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" "amdgpu-work-item-id-x" "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" }
;.
; ATTRIBUTOR_HSA: attributes #[[ATTR0:[0-9]+]] = { nounwind readnone speculatable willreturn }
-; ATTRIBUTOR_HSA: attributes #[[ATTR1]] = { nounwind "target-cpu"="fiji" "uniform-work-group-size"="false" }
-; ATTRIBUTOR_HSA: attributes #[[ATTR2]] = { noreturn nounwind readnone "target-cpu"="fiji" "uniform-work-group-size"="false" }
-; ATTRIBUTOR_HSA: attributes #[[ATTR3]] = { noreturn nounwind "target-cpu"="fiji" "uniform-work-group-size"="false" }
-; ATTRIBUTOR_HSA: attributes #[[ATTR4]] = { nounwind "amdgpu-queue-ptr" "target-cpu"="fiji" "uniform-work-group-size"="false" }
-; ATTRIBUTOR_HSA: attributes #[[ATTR5]] = { nounwind "target-cpu"="gfx900" "uniform-work-group-size"="false" }
-; ATTRIBUTOR_HSA: attributes #[[ATTR6]] = { nounwind "amdgpu-dispatch-id" "amdgpu-dispatch-ptr" "amdgpu-implicitarg-ptr" "amdgpu-queue-ptr" "amdgpu-work-group-id-x" "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" "amdgpu-work-item-id-x" "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" "uniform-work-group-size"="false" }
-; ATTRIBUTOR_HSA: attributes #[[ATTR7]] = { nounwind "uniform-work-group-size"="false" }
-; ATTRIBUTOR_HSA: attributes #[[ATTR8]] = { nounwind "amdgpu-dispatch-id" "amdgpu-dispatch-ptr" "amdgpu-implicitarg-ptr" "amdgpu-queue-ptr" "amdgpu-work-group-id-x" "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" "amdgpu-work-item-id-x" "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" }
-; ATTRIBUTOR_HSA: attributes #[[ATTR9]] = { nounwind }
-; ATTRIBUTOR_HSA: attributes #[[ATTR10]] = { noreturn nounwind }
+; ATTRIBUTOR_HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-work-item-id-x" "target-cpu"="fiji" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-work-item-id-y" "target-cpu"="fiji" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR3]] = { nounwind "amdgpu-work-item-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR4]] = { nounwind "amdgpu-work-group-id-x" "target-cpu"="fiji" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR5]] = { nounwind "amdgpu-work-group-id-y" "target-cpu"="fiji" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR6]] = { nounwind "amdgpu-work-group-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR7]] = { nounwind "amdgpu-dispatch-ptr" "target-cpu"="fiji" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR8]] = { nounwind "amdgpu-queue-ptr" "target-cpu"="fiji" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR9]] = { nounwind "amdgpu-dispatch-id" "target-cpu"="fiji" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR10]] = { nounwind "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR11]] = { nounwind "target-cpu"="fiji" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR12]] = { nounwind "target-cpu"="gfx900" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR13]] = { nounwind "amdgpu-queue-ptr" "target-cpu"="gfx900" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR14]] = { nounwind "amdgpu-implicitarg-ptr" "target-cpu"="fiji" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR15]] = { nounwind "amdgpu-dispatch-id" "amdgpu-dispatch-ptr" "amdgpu-implicitarg-ptr" "amdgpu-queue-ptr" "amdgpu-work-group-id-x" "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" "amdgpu-work-item-id-x" "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR16]] = { nounwind "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR17]] = { nounwind "amdgpu-dispatch-id" "amdgpu-dispatch-ptr" "amdgpu-implicitarg-ptr" "amdgpu-queue-ptr" "amdgpu-work-group-id-x" "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" "amdgpu-work-item-id-x" "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR18]] = { nounwind }
;.
diff --git a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
index c9e115cf7f90..46c73b81afff 100644
--- a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
+++ b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
@@ -405,16 +405,12 @@ define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #1 {
}
define amdgpu_kernel void @use_is_shared(i8* %ptr) #1 {
-; AKF_HSA-LABEL: define {{[^@]+}}@use_is_shared
-; AKF_HSA-SAME: (i8* [[PTR:%.*]]) #[[ATTR11]] {
-; AKF_HSA-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(i8* [[PTR]])
-; AKF_HSA-NEXT: [[EXT:%.*]] = zext i1 [[IS_SHARED]] to i32
-; AKF_HSA-NEXT: store i32 [[EXT]], i32 addrspace(1)* undef, align 4
-; AKF_HSA-NEXT: ret void
-;
-; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_is_shared
-; ATTRIBUTOR_HSA-SAME: (i8* [[PTR:%.*]]) #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: ret void
+; HSA-LABEL: define {{[^@]+}}@use_is_shared
+; HSA-SAME: (i8* [[PTR:%.*]]) #[[ATTR11]] {
+; HSA-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(i8* [[PTR]])
+; HSA-NEXT: [[EXT:%.*]] = zext i1 [[IS_SHARED]] to i32
+; HSA-NEXT: store i32 [[EXT]], i32 addrspace(1)* undef, align 4
+; HSA-NEXT: ret void
;
%is.shared = call i1 @llvm.amdgcn.is.shared(i8* %ptr)
%ext = zext i1 %is.shared to i32
@@ -423,16 +419,12 @@ define amdgpu_kernel void @use_is_shared(i8* %ptr) #1 {
}
define amdgpu_kernel void @use_is_private(i8* %ptr) #1 {
-; AKF_HSA-LABEL: define {{[^@]+}}@use_is_private
-; AKF_HSA-SAME: (i8* [[PTR:%.*]]) #[[ATTR11]] {
-; AKF_HSA-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(i8* [[PTR]])
-; AKF_HSA-NEXT: [[EXT:%.*]] = zext i1 [[IS_PRIVATE]] to i32
-; AKF_HSA-NEXT: store i32 [[EXT]], i32 addrspace(1)* undef, align 4
-; AKF_HSA-NEXT: ret void
-;
-; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_is_private
-; ATTRIBUTOR_HSA-SAME: (i8* [[PTR:%.*]]) #[[ATTR1]] {
-; ATTRIBUTOR_HSA-NEXT: ret void
+; HSA-LABEL: define {{[^@]+}}@use_is_private
+; HSA-SAME: (i8* [[PTR:%.*]]) #[[ATTR11]] {
+; HSA-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(i8* [[PTR]])
+; HSA-NEXT: [[EXT:%.*]] = zext i1 [[IS_PRIVATE]] to i32
+; HSA-NEXT: store i32 [[EXT]], i32 addrspace(1)* undef, align 4
+; HSA-NEXT: ret void
;
%is.private = call i1 @llvm.amdgcn.is.private(i8* %ptr)
%ext = zext i1 %is.private to i32
diff --git a/llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll b/llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll
index 94b5f80f053c..e6ee17da783a 100644
--- a/llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll
@@ -21,7 +21,10 @@ define internal void @direct() {
;
; ATTRIBUTOR_GCN-LABEL: define {{[^@]+}}@direct
; ATTRIBUTOR_GCN-SAME: () #[[ATTR0]] {
-; ATTRIBUTOR_GCN-NEXT: call void @indirect()
+; ATTRIBUTOR_GCN-NEXT: [[FPTR:%.*]] = alloca void ()*, align 8
+; ATTRIBUTOR_GCN-NEXT: store void ()* @indirect, void ()** [[FPTR]], align 8
+; ATTRIBUTOR_GCN-NEXT: [[FP:%.*]] = load void ()*, void ()** [[FPTR]], align 8
+; ATTRIBUTOR_GCN-NEXT: call void [[FP]]()
; ATTRIBUTOR_GCN-NEXT: ret void
;
%fptr = alloca void()*
diff --git a/llvm/test/CodeGen/AMDGPU/uniform-work-group-attribute-missing.ll b/llvm/test/CodeGen/AMDGPU/uniform-work-group-attribute-missing.ll
index 6bef52f5d726..0258169d78f1 100644
--- a/llvm/test/CodeGen/AMDGPU/uniform-work-group-attribute-missing.ll
+++ b/llvm/test/CodeGen/AMDGPU/uniform-work-group-attribute-missing.ll
@@ -27,8 +27,8 @@ define amdgpu_kernel void @kernel1() #1 {
; AKF_CHECK-NEXT: ret void
;
; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@kernel1
-; ATTRIBUTOR_CHECK-SAME: () #[[ATTR1:[0-9]+]] {
-; ATTRIBUTOR_CHECK-NEXT: call void @foo() #[[ATTR2:[0-9]+]]
+; ATTRIBUTOR_CHECK-SAME: () #[[ATTR0]] {
+; ATTRIBUTOR_CHECK-NEXT: call void @foo()
; ATTRIBUTOR_CHECK-NEXT: ret void
;
call void @foo()
@@ -40,7 +40,5 @@ attributes #0 = { "uniform-work-group-size"="true" }
; AKF_CHECK: attributes #[[ATTR0]] = { "uniform-work-group-size"="false" }
; AKF_CHECK: attributes #[[ATTR1]] = { "amdgpu-calls" "uniform-work-group-size"="false" }
;.
-; ATTRIBUTOR_CHECK: attributes #[[ATTR0]] = { nounwind writeonly "uniform-work-group-size"="false" }
-; ATTRIBUTOR_CHECK: attributes #[[ATTR1]] = { "uniform-work-group-size"="false" }
-; ATTRIBUTOR_CHECK: attributes #[[ATTR2]] = { nounwind writeonly }
+; ATTRIBUTOR_CHECK: attributes #[[ATTR0]] = { "uniform-work-group-size"="false" }
;.
diff --git a/llvm/test/CodeGen/AMDGPU/uniform-work-group-multistep.ll b/llvm/test/CodeGen/AMDGPU/uniform-work-group-multistep.ll
index a46b749526ce..6164301f8e1c 100644
--- a/llvm/test/CodeGen/AMDGPU/uniform-work-group-multistep.ll
+++ b/llvm/test/CodeGen/AMDGPU/uniform-work-group-multistep.ll
@@ -7,15 +7,10 @@
; CHECK: @[[G2:[a-zA-Z0-9_$"\\.-]+]] = global i32 0
;.
define weak void @weak() {
-; AKF_CHECK-LABEL: define {{[^@]+}}@weak
-; AKF_CHECK-SAME: () #[[ATTR0:[0-9]+]] {
-; AKF_CHECK-NEXT: call void @internal1()
-; AKF_CHECK-NEXT: ret void
-;
-; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@weak
-; ATTRIBUTOR_CHECK-SAME: () #[[ATTR0:[0-9]+]] {
-; ATTRIBUTOR_CHECK-NEXT: call void @internal1() #[[ATTR5:[0-9]+]]
-; ATTRIBUTOR_CHECK-NEXT: ret void
+; CHECK-LABEL: define {{[^@]+}}@weak
+; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: call void @internal1()
+; CHECK-NEXT: ret void
;
call void @internal1()
ret void
@@ -24,17 +19,11 @@ define weak void @weak() {
@G1 = global i32* null
define internal void @internal1() {
-; AKF_CHECK-LABEL: define {{[^@]+}}@internal1
-; AKF_CHECK-SAME: () #[[ATTR0]] {
-; AKF_CHECK-NEXT: [[TMP1:%.*]] = load i32*, i32** @G1, align 8
-; AKF_CHECK-NEXT: store i32 0, i32* [[TMP1]], align 4
-; AKF_CHECK-NEXT: ret void
-;
-; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@internal1
-; ATTRIBUTOR_CHECK-SAME: () #[[ATTR1:[0-9]+]] {
-; ATTRIBUTOR_CHECK-NEXT: [[TMP1:%.*]] = load i32*, i32** @G1, align 8
-; ATTRIBUTOR_CHECK-NEXT: store i32 0, i32* [[TMP1]], align 4
-; ATTRIBUTOR_CHECK-NEXT: ret void
+; CHECK-LABEL: define {{[^@]+}}@internal1
+; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-NEXT: [[TMP1:%.*]] = load i32*, i32** @G1, align 8
+; CHECK-NEXT: store i32 0, i32* [[TMP1]], align 4
+; CHECK-NEXT: ret void
;
%1 = load i32*, i32** @G1
store i32 0, i32* %1
@@ -42,15 +31,10 @@ define internal void @internal1() {
}
define amdgpu_kernel void @kernel1() #0 {
-; AKF_CHECK-LABEL: define {{[^@]+}}@kernel1
-; AKF_CHECK-SAME: () #[[ATTR1:[0-9]+]] {
-; AKF_CHECK-NEXT: call void @weak()
-; AKF_CHECK-NEXT: ret void
-;
-; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@kernel1
-; ATTRIBUTOR_CHECK-SAME: () #[[ATTR2:[0-9]+]] {
-; ATTRIBUTOR_CHECK-NEXT: call void @weak()
-; ATTRIBUTOR_CHECK-NEXT: ret void
+; CHECK-LABEL: define {{[^@]+}}@kernel1
+; CHECK-SAME: () #[[ATTR1:[0-9]+]] {
+; CHECK-NEXT: call void @weak()
+; CHECK-NEXT: ret void
;
call void @weak()
ret void
@@ -72,13 +56,13 @@ define internal void @internal3() {
; AKF_CHECK-NEXT: ret void
;
; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@internal3
-; ATTRIBUTOR_CHECK-SAME: () #[[ATTR3:[0-9]+]] {
+; ATTRIBUTOR_CHECK-SAME: () #[[ATTR1]] {
; ATTRIBUTOR_CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @G2, align 4
; ATTRIBUTOR_CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
; ATTRIBUTOR_CHECK-NEXT: br i1 [[TMP2]], label [[TMP3:%.*]], label [[TMP4:%.*]]
; ATTRIBUTOR_CHECK: 3:
-; ATTRIBUTOR_CHECK-NEXT: call void @internal4() #[[ATTR6:[0-9]+]]
-; ATTRIBUTOR_CHECK-NEXT: call void @internal3() #[[ATTR7:[0-9]+]]
+; ATTRIBUTOR_CHECK-NEXT: call void @internal4()
+; ATTRIBUTOR_CHECK-NEXT: call void @internal3()
; ATTRIBUTOR_CHECK-NEXT: br label [[TMP4]]
; ATTRIBUTOR_CHECK: 4:
; ATTRIBUTOR_CHECK-NEXT: ret void
@@ -101,7 +85,7 @@ define internal void @internal4() {
; AKF_CHECK-NEXT: ret void
;
; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@internal4
-; ATTRIBUTOR_CHECK-SAME: () #[[ATTR4:[0-9]+]] {
+; ATTRIBUTOR_CHECK-SAME: () #[[ATTR1]] {
; ATTRIBUTOR_CHECK-NEXT: store i32 1, i32* @G2, align 4
; ATTRIBUTOR_CHECK-NEXT: ret void
;
@@ -116,8 +100,8 @@ define internal void @internal2() {
; AKF_CHECK-NEXT: ret void
;
; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@internal2
-; ATTRIBUTOR_CHECK-SAME: () #[[ATTR3]] {
-; ATTRIBUTOR_CHECK-NEXT: call void @internal3() #[[ATTR7]]
+; ATTRIBUTOR_CHECK-SAME: () #[[ATTR1]] {
+; ATTRIBUTOR_CHECK-NEXT: call void @internal3()
; ATTRIBUTOR_CHECK-NEXT: ret void
;
call void @internal3()
@@ -125,15 +109,10 @@ define internal void @internal2() {
}
define amdgpu_kernel void @kernel2() #0 {
-; AKF_CHECK-LABEL: define {{[^@]+}}@kernel2
-; AKF_CHECK-SAME: () #[[ATTR1]] {
-; AKF_CHECK-NEXT: call void @internal2()
-; AKF_CHECK-NEXT: ret void
-;
-; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@kernel2
-; ATTRIBUTOR_CHECK-SAME: () #[[ATTR2]] {
-; ATTRIBUTOR_CHECK-NEXT: call void @internal2() #[[ATTR5]]
-; ATTRIBUTOR_CHECK-NEXT: ret void
+; CHECK-LABEL: define {{[^@]+}}@kernel2
+; CHECK-SAME: () #[[ATTR1]] {
+; CHECK-NEXT: call void @internal2()
+; CHECK-NEXT: ret void
;
call void @internal2()
ret void
@@ -147,11 +126,5 @@ attributes #0 = { "uniform-work-group-size"="true" }
; AKF_CHECK: attributes #[[ATTR2]] = { "uniform-work-group-size"="true" }
;.
; ATTRIBUTOR_CHECK: attributes #[[ATTR0]] = { "uniform-work-group-size"="false" }
-; ATTRIBUTOR_CHECK: attributes #[[ATTR1]] = { nofree nosync nounwind willreturn "uniform-work-group-size"="false" }
-; ATTRIBUTOR_CHECK: attributes #[[ATTR2]] = { "uniform-work-group-size"="true" }
-; ATTRIBUTOR_CHECK: attributes #[[ATTR3]] = { nofree nosync nounwind "uniform-work-group-size"="true" }
-; ATTRIBUTOR_CHECK: attributes #[[ATTR4]] = { nofree nosync nounwind willreturn writeonly "uniform-work-group-size"="true" }
-; ATTRIBUTOR_CHECK: attributes #[[ATTR5]] = { nounwind }
-; ATTRIBUTOR_CHECK: attributes #[[ATTR6]] = { nofree nosync nounwind willreturn writeonly }
-; ATTRIBUTOR_CHECK: attributes #[[ATTR7]] = { nofree nosync nounwind }
+; ATTRIBUTOR_CHECK: attributes #[[ATTR1]] = { "uniform-work-group-size"="true" }
;.
diff --git a/llvm/test/CodeGen/AMDGPU/uniform-work-group-nested-function-calls.ll b/llvm/test/CodeGen/AMDGPU/uniform-work-group-nested-function-calls.ll
index e9991dc121c6..935e16ec0ac4 100644
--- a/llvm/test/CodeGen/AMDGPU/uniform-work-group-nested-function-calls.ll
+++ b/llvm/test/CodeGen/AMDGPU/uniform-work-group-nested-function-calls.ll
@@ -35,7 +35,7 @@ define void @func2() #1 {
;
; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@func2
; ATTRIBUTOR_CHECK-SAME: () #[[ATTR0]] {
-; ATTRIBUTOR_CHECK-NEXT: call void @func1() #[[ATTR2:[0-9]+]]
+; ATTRIBUTOR_CHECK-NEXT: call void @func1()
; ATTRIBUTOR_CHECK-NEXT: ret void
;
call void @func1()
@@ -50,7 +50,7 @@ define amdgpu_kernel void @kernel3() #2 {
;
; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@kernel3
; ATTRIBUTOR_CHECK-SAME: () #[[ATTR1:[0-9]+]] {
-; ATTRIBUTOR_CHECK-NEXT: call void @func2() #[[ATTR2]]
+; ATTRIBUTOR_CHECK-NEXT: call void @func2()
; ATTRIBUTOR_CHECK-NEXT: ret void
;
call void @func2()
@@ -62,7 +62,6 @@ attributes #2 = { "uniform-work-group-size"="true" }
; AKF_CHECK: attributes #[[ATTR0]] = { "uniform-work-group-size"="true" }
; AKF_CHECK: attributes #[[ATTR1]] = { "amdgpu-calls" "uniform-work-group-size"="true" }
;.
-; ATTRIBUTOR_CHECK: attributes #[[ATTR0]] = { nounwind writeonly "uniform-work-group-size"="false" }
+; ATTRIBUTOR_CHECK: attributes #[[ATTR0]] = { "uniform-work-group-size"="false" }
; ATTRIBUTOR_CHECK: attributes #[[ATTR1]] = { "uniform-work-group-size"="true" }
-; ATTRIBUTOR_CHECK: attributes #[[ATTR2]] = { nounwind writeonly }
;.
diff --git a/llvm/test/CodeGen/AMDGPU/uniform-work-group-prevent-attribute-propagation.ll b/llvm/test/CodeGen/AMDGPU/uniform-work-group-prevent-attribute-propagation.ll
index d22f1e2a977b..5815ed707826 100644
--- a/llvm/test/CodeGen/AMDGPU/uniform-work-group-prevent-attribute-propagation.ll
+++ b/llvm/test/CodeGen/AMDGPU/uniform-work-group-prevent-attribute-propagation.ll
@@ -22,15 +22,10 @@ define void @func() #0 {
}
define amdgpu_kernel void @kernel1() #1 {
-; AKF_CHECK-LABEL: define {{[^@]+}}@kernel1
-; AKF_CHECK-SAME: () #[[ATTR1:[0-9]+]] {
-; AKF_CHECK-NEXT: call void @func()
-; AKF_CHECK-NEXT: ret void
-;
-; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@kernel1
-; ATTRIBUTOR_CHECK-SAME: () #[[ATTR1:[0-9]+]] {
-; ATTRIBUTOR_CHECK-NEXT: call void @func() #[[ATTR3:[0-9]+]]
-; ATTRIBUTOR_CHECK-NEXT: ret void
+; CHECK-LABEL: define {{[^@]+}}@kernel1
+; CHECK-SAME: () #[[ATTR1:[0-9]+]] {
+; CHECK-NEXT: call void @func()
+; CHECK-NEXT: ret void
;
call void @func()
ret void
@@ -43,8 +38,8 @@ define amdgpu_kernel void @kernel2() #2 {
; AKF_CHECK-NEXT: ret void
;
; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@kernel2
-; ATTRIBUTOR_CHECK-SAME: () #[[ATTR2:[0-9]+]] {
-; ATTRIBUTOR_CHECK-NEXT: call void @func() #[[ATTR3]]
+; ATTRIBUTOR_CHECK-SAME: () #[[ATTR0]] {
+; ATTRIBUTOR_CHECK-NEXT: call void @func()
; ATTRIBUTOR_CHECK-NEXT: ret void
;
call void @func()
@@ -58,8 +53,6 @@ attributes #1 = { "uniform-work-group-size"="true" }
; AKF_CHECK: attributes #[[ATTR1]] = { "amdgpu-calls" "uniform-work-group-size"="true" }
; AKF_CHECK: attributes #[[ATTR2]] = { "amdgpu-calls" "uniform-work-group-size"="false" }
;.
-; ATTRIBUTOR_CHECK: attributes #[[ATTR0]] = { nounwind writeonly "uniform-work-group-size"="false" }
+; ATTRIBUTOR_CHECK: attributes #[[ATTR0]] = { "uniform-work-group-size"="false" }
; ATTRIBUTOR_CHECK: attributes #[[ATTR1]] = { "uniform-work-group-size"="true" }
-; ATTRIBUTOR_CHECK: attributes #[[ATTR2]] = { "uniform-work-group-size"="false" }
-; ATTRIBUTOR_CHECK: attributes #[[ATTR3]] = { nounwind writeonly }
;.
diff --git a/llvm/test/CodeGen/AMDGPU/uniform-work-group-propagate-attribute.ll b/llvm/test/CodeGen/AMDGPU/uniform-work-group-propagate-attribute.ll
index 04ee89da28d2..a93986716359 100644
--- a/llvm/test/CodeGen/AMDGPU/uniform-work-group-propagate-attribute.ll
+++ b/llvm/test/CodeGen/AMDGPU/uniform-work-group-propagate-attribute.ll
@@ -19,15 +19,10 @@ define void @func() #0 {
}
define amdgpu_kernel void @kernel1() #1 {
-; AKF_CHECK-LABEL: define {{[^@]+}}@kernel1
-; AKF_CHECK-SAME: () #[[ATTR1:[0-9]+]] {
-; AKF_CHECK-NEXT: call void @func()
-; AKF_CHECK-NEXT: ret void
-;
-; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@kernel1
-; ATTRIBUTOR_CHECK-SAME: () #[[ATTR1:[0-9]+]] {
-; ATTRIBUTOR_CHECK-NEXT: call void @func() #[[ATTR4:[0-9]+]]
-; ATTRIBUTOR_CHECK-NEXT: ret void
+; CHECK-LABEL: define {{[^@]+}}@kernel1
+; CHECK-SAME: () #[[ATTR1:[0-9]+]] {
+; CHECK-NEXT: call void @func()
+; CHECK-NEXT: ret void
;
call void @func()
ret void
@@ -35,30 +30,20 @@ define amdgpu_kernel void @kernel1() #1 {
; External declaration of a function
define weak_odr void @weak_func() #0 {
-; AKF_CHECK-LABEL: define {{[^@]+}}@weak_func
-; AKF_CHECK-SAME: () #[[ATTR0]] {
-; AKF_CHECK-NEXT: store i32 0, i32* @x, align 4
-; AKF_CHECK-NEXT: ret void
-;
-; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@weak_func
-; ATTRIBUTOR_CHECK-SAME: () #[[ATTR2:[0-9]+]] {
-; ATTRIBUTOR_CHECK-NEXT: store i32 0, i32* @x, align 4
-; ATTRIBUTOR_CHECK-NEXT: ret void
+; CHECK-LABEL: define {{[^@]+}}@weak_func
+; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-NEXT: store i32 0, i32* @x, align 4
+; CHECK-NEXT: ret void
;
store i32 0, i32* @x
ret void
}
define amdgpu_kernel void @kernel2() #2 {
-; AKF_CHECK-LABEL: define {{[^@]+}}@kernel2
-; AKF_CHECK-SAME: () #[[ATTR2:[0-9]+]] {
-; AKF_CHECK-NEXT: call void @weak_func()
-; AKF_CHECK-NEXT: ret void
-;
-; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@kernel2
-; ATTRIBUTOR_CHECK-SAME: () #[[ATTR3:[0-9]+]] {
-; ATTRIBUTOR_CHECK-NEXT: call void @weak_func() #[[ATTR5:[0-9]+]]
-; ATTRIBUTOR_CHECK-NEXT: ret void
+; CHECK-LABEL: define {{[^@]+}}@kernel2
+; CHECK-SAME: () #[[ATTR2:[0-9]+]] {
+; CHECK-NEXT: call void @weak_func()
+; CHECK-NEXT: ret void
;
call void @weak_func()
ret void
@@ -72,10 +57,7 @@ attributes #2 = { "uniform-work-group-size"="true" }
; AKF_CHECK: attributes #[[ATTR1]] = { "amdgpu-calls" "uniform-work-group-size"="false" }
; AKF_CHECK: attributes #[[ATTR2]] = { "amdgpu-calls" "uniform-work-group-size"="true" }
;.
-; ATTRIBUTOR_CHECK: attributes #[[ATTR0]] = { nounwind writeonly "uniform-work-group-size"="false" }
+; ATTRIBUTOR_CHECK: attributes #[[ATTR0]] = { nounwind "uniform-work-group-size"="false" }
; ATTRIBUTOR_CHECK: attributes #[[ATTR1]] = { "uniform-work-group-size"="false" }
-; ATTRIBUTOR_CHECK: attributes #[[ATTR2]] = { nounwind "uniform-work-group-size"="false" }
-; ATTRIBUTOR_CHECK: attributes #[[ATTR3]] = { "uniform-work-group-size"="true" }
-; ATTRIBUTOR_CHECK: attributes #[[ATTR4]] = { nounwind writeonly }
-; ATTRIBUTOR_CHECK: attributes #[[ATTR5]] = { nounwind }
+; ATTRIBUTOR_CHECK: attributes #[[ATTR2]] = { "uniform-work-group-size"="true" }
;.
diff --git a/llvm/test/CodeGen/AMDGPU/uniform-work-group-recursion-test.ll b/llvm/test/CodeGen/AMDGPU/uniform-work-group-recursion-test.ll
index c6e276c9d11b..8fe401e1bb86 100644
--- a/llvm/test/CodeGen/AMDGPU/uniform-work-group-recursion-test.ll
+++ b/llvm/test/CodeGen/AMDGPU/uniform-work-group-recursion-test.ll
@@ -6,39 +6,22 @@
; Test to generate fibonacci numbers
define i32 @fib(i32 %n) #0 {
-; AKF_CHECK-LABEL: define {{[^@]+}}@fib
-; AKF_CHECK-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
-; AKF_CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[N]], 0
-; AKF_CHECK-NEXT: br i1 [[CMP1]], label [[EXIT:%.*]], label [[CONT1:%.*]]
-; AKF_CHECK: cont1:
-; AKF_CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[N]], 1
-; AKF_CHECK-NEXT: br i1 [[CMP2]], label [[EXIT]], label [[CONT2:%.*]]
-; AKF_CHECK: cont2:
-; AKF_CHECK-NEXT: [[NM1:%.*]] = sub i32 [[N]], 1
-; AKF_CHECK-NEXT: [[FIBM1:%.*]] = call i32 @fib(i32 [[NM1]])
-; AKF_CHECK-NEXT: [[NM2:%.*]] = sub i32 [[N]], 2
-; AKF_CHECK-NEXT: [[FIBM2:%.*]] = call i32 @fib(i32 [[NM2]])
-; AKF_CHECK-NEXT: [[RETVAL:%.*]] = add i32 [[FIBM1]], [[FIBM2]]
-; AKF_CHECK-NEXT: ret i32 [[RETVAL]]
-; AKF_CHECK: exit:
-; AKF_CHECK-NEXT: ret i32 1
-;
-; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@fib
-; ATTRIBUTOR_CHECK-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
-; ATTRIBUTOR_CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[N]], 0
-; ATTRIBUTOR_CHECK-NEXT: br i1 [[CMP1]], label [[EXIT:%.*]], label [[CONT1:%.*]]
-; ATTRIBUTOR_CHECK: cont1:
-; ATTRIBUTOR_CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[N]], 1
-; ATTRIBUTOR_CHECK-NEXT: br i1 [[CMP2]], label [[EXIT]], label [[CONT2:%.*]]
-; ATTRIBUTOR_CHECK: cont2:
-; ATTRIBUTOR_CHECK-NEXT: [[NM1:%.*]] = sub i32 [[N]], 1
-; ATTRIBUTOR_CHECK-NEXT: [[FIBM1:%.*]] = call i32 @fib(i32 [[NM1]]) #[[ATTR3:[0-9]+]]
-; ATTRIBUTOR_CHECK-NEXT: [[NM2:%.*]] = sub i32 [[N]], 2
-; ATTRIBUTOR_CHECK-NEXT: [[FIBM2:%.*]] = call i32 @fib(i32 [[NM2]]) #[[ATTR3]]
-; ATTRIBUTOR_CHECK-NEXT: [[RETVAL:%.*]] = add i32 [[FIBM1]], [[FIBM2]]
-; ATTRIBUTOR_CHECK-NEXT: ret i32 [[RETVAL]]
-; ATTRIBUTOR_CHECK: exit:
-; ATTRIBUTOR_CHECK-NEXT: ret i32 1
+; CHECK-LABEL: define {{[^@]+}}@fib
+; CHECK-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[N]], 0
+; CHECK-NEXT: br i1 [[CMP1]], label [[EXIT:%.*]], label [[CONT1:%.*]]
+; CHECK: cont1:
+; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[N]], 1
+; CHECK-NEXT: br i1 [[CMP2]], label [[EXIT]], label [[CONT2:%.*]]
+; CHECK: cont2:
+; CHECK-NEXT: [[NM1:%.*]] = sub i32 [[N]], 1
+; CHECK-NEXT: [[FIBM1:%.*]] = call i32 @fib(i32 [[NM1]])
+; CHECK-NEXT: [[NM2:%.*]] = sub i32 [[N]], 2
+; CHECK-NEXT: [[FIBM2:%.*]] = call i32 @fib(i32 [[NM2]])
+; CHECK-NEXT: [[RETVAL:%.*]] = add i32 [[FIBM1]], [[FIBM2]]
+; CHECK-NEXT: ret i32 [[RETVAL]]
+; CHECK: exit:
+; CHECK-NEXT: ret i32 1
;
%cmp1 = icmp eq i32 %n, 0
br i1 %cmp1, label %exit, label %cont1
@@ -87,9 +70,9 @@ define internal i32 @fib_internal(i32 %n) #0 {
; ATTRIBUTOR_CHECK-NEXT: br i1 [[CMP2]], label [[EXIT]], label [[CONT2:%.*]]
; ATTRIBUTOR_CHECK: cont2:
; ATTRIBUTOR_CHECK-NEXT: [[NM1:%.*]] = sub i32 [[N]], 1
-; ATTRIBUTOR_CHECK-NEXT: [[FIBM1:%.*]] = call i32 @fib_internal(i32 [[NM1]]) #[[ATTR4:[0-9]+]]
+; ATTRIBUTOR_CHECK-NEXT: [[FIBM1:%.*]] = call i32 @fib_internal(i32 [[NM1]])
; ATTRIBUTOR_CHECK-NEXT: [[NM2:%.*]] = sub i32 [[N]], 2
-; ATTRIBUTOR_CHECK-NEXT: [[FIBM2:%.*]] = call i32 @fib_internal(i32 [[NM2]]) #[[ATTR4]]
+; ATTRIBUTOR_CHECK-NEXT: [[FIBM2:%.*]] = call i32 @fib_internal(i32 [[NM2]])
; ATTRIBUTOR_CHECK-NEXT: [[RETVAL:%.*]] = add i32 [[FIBM1]], [[FIBM2]]
; ATTRIBUTOR_CHECK-NEXT: ret i32 [[RETVAL]]
; ATTRIBUTOR_CHECK: exit:
@@ -126,8 +109,8 @@ define amdgpu_kernel void @kernel(i32 addrspace(1)* %m) #1 {
;
; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@kernel
; ATTRIBUTOR_CHECK-SAME: (i32 addrspace(1)* [[M:%.*]]) #[[ATTR2:[0-9]+]] {
-; ATTRIBUTOR_CHECK-NEXT: [[R:%.*]] = call i32 @fib(i32 5) #[[ATTR3]]
-; ATTRIBUTOR_CHECK-NEXT: [[R2:%.*]] = call i32 @fib_internal(i32 noundef 5) #[[ATTR3]]
+; ATTRIBUTOR_CHECK-NEXT: [[R:%.*]] = call i32 @fib(i32 5)
+; ATTRIBUTOR_CHECK-NEXT: [[R2:%.*]] = call i32 @fib_internal(i32 5)
; ATTRIBUTOR_CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[M]], align 4
; ATTRIBUTOR_CHECK-NEXT: store i32 [[R2]], i32 addrspace(1)* [[M]], align 4
; ATTRIBUTOR_CHECK-NEXT: ret void
@@ -149,8 +132,6 @@ attributes #1 = { "uniform-work-group-size"="true" }
; AKF_CHECK: attributes #[[ATTR1]] = { "amdgpu-calls" "uniform-work-group-size"="true" }
;.
; ATTRIBUTOR_CHECK: attributes #[[ATTR0]] = { nounwind readnone "uniform-work-group-size"="false" }
-; ATTRIBUTOR_CHECK: attributes #[[ATTR1]] = { nofree nosync nounwind readnone "uniform-work-group-size"="true" }
+; ATTRIBUTOR_CHECK: attributes #[[ATTR1]] = { nounwind readnone "uniform-work-group-size"="true" }
; ATTRIBUTOR_CHECK: attributes #[[ATTR2]] = { "uniform-work-group-size"="true" }
-; ATTRIBUTOR_CHECK: attributes #[[ATTR3]] = { nounwind readnone }
-; ATTRIBUTOR_CHECK: attributes #[[ATTR4]] = { nofree nounwind readnone }
;.
diff --git a/llvm/test/CodeGen/AMDGPU/uniform-work-group-test.ll b/llvm/test/CodeGen/AMDGPU/uniform-work-group-test.ll
index 9aee29be8dc2..b8869c286688 100644
--- a/llvm/test/CodeGen/AMDGPU/uniform-work-group-test.ll
+++ b/llvm/test/CodeGen/AMDGPU/uniform-work-group-test.ll
@@ -27,17 +27,11 @@ define void @func4() {
}
define void @func2() #0 {
-; AKF_CHECK-LABEL: define {{[^@]+}}@func2
-; AKF_CHECK-SAME: () #[[ATTR0]] {
-; AKF_CHECK-NEXT: call void @func4()
-; AKF_CHECK-NEXT: call void @func1()
-; AKF_CHECK-NEXT: ret void
-;
-; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@func2
-; ATTRIBUTOR_CHECK-SAME: () #[[ATTR0]] {
-; ATTRIBUTOR_CHECK-NEXT: call void @func4() #[[ATTR2:[0-9]+]]
-; ATTRIBUTOR_CHECK-NEXT: call void @func1() #[[ATTR2]]
-; ATTRIBUTOR_CHECK-NEXT: ret void
+; CHECK-LABEL: define {{[^@]+}}@func2
+; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-NEXT: call void @func4()
+; CHECK-NEXT: call void @func1()
+; CHECK-NEXT: ret void
;
call void @func4()
call void @func1()
@@ -45,15 +39,10 @@ define void @func2() #0 {
}
define void @func3() {
-; AKF_CHECK-LABEL: define {{[^@]+}}@func3
-; AKF_CHECK-SAME: () #[[ATTR0]] {
-; AKF_CHECK-NEXT: call void @func1()
-; AKF_CHECK-NEXT: ret void
-;
-; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@func3
-; ATTRIBUTOR_CHECK-SAME: () #[[ATTR0]] {
-; ATTRIBUTOR_CHECK-NEXT: call void @func1() #[[ATTR2]]
-; ATTRIBUTOR_CHECK-NEXT: ret void
+; CHECK-LABEL: define {{[^@]+}}@func3
+; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-NEXT: call void @func1()
+; CHECK-NEXT: ret void
;
call void @func1()
ret void
@@ -67,9 +56,9 @@ define amdgpu_kernel void @kernel3() #0 {
; AKF_CHECK-NEXT: ret void
;
; ATTRIBUTOR_CHECK-LABEL: define {{[^@]+}}@kernel3
-; ATTRIBUTOR_CHECK-SAME: () #[[ATTR1:[0-9]+]] {
-; ATTRIBUTOR_CHECK-NEXT: call void @func2() #[[ATTR2]]
-; ATTRIBUTOR_CHECK-NEXT: call void @func3() #[[ATTR2]]
+; ATTRIBUTOR_CHECK-SAME: () #[[ATTR0]] {
+; ATTRIBUTOR_CHECK-NEXT: call void @func2()
+; ATTRIBUTOR_CHECK-NEXT: call void @func3()
; ATTRIBUTOR_CHECK-NEXT: ret void
;
call void @func2()
@@ -82,7 +71,5 @@ attributes #0 = { "uniform-work-group-size"="false" }
; AKF_CHECK: attributes #[[ATTR0]] = { "uniform-work-group-size"="false" }
; AKF_CHECK: attributes #[[ATTR1]] = { "amdgpu-calls" "uniform-work-group-size"="false" }
;.
-; ATTRIBUTOR_CHECK: attributes #[[ATTR0]] = { nounwind writeonly "uniform-work-group-size"="false" }
-; ATTRIBUTOR_CHECK: attributes #[[ATTR1]] = { "uniform-work-group-size"="false" }
-; ATTRIBUTOR_CHECK: attributes #[[ATTR2]] = { nounwind writeonly }
+; ATTRIBUTOR_CHECK: attributes #[[ATTR0]] = { "uniform-work-group-size"="false" }
;.
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