[llvm] 9b9e7f6 - [docs, AMDGPU] Fix typo in dwarf register number mapping

[via llvm-commits]

Author: RamNalamothu
Date: 2021-08-26T23:55:29+05:30
New Revision: 9b9e7f6f4e05baa99a795e0cce60ba86091acc9a

URL: https://github.com/llvm/llvm-project/commit/9b9e7f6f4e05baa99a795e0cce60ba86091acc9a
DIFF: https://github.com/llvm/llvm-project/commit/9b9e7f6f4e05baa99a795e0cce60ba86091acc9a.diff

LOG: [docs, AMDGPU] Fix typo in dwarf register number mapping

Reviewed By: xgupta

Differential Revision: https://reviews.llvm.org/D108557

Added: 
    

Modified: 
    llvm/docs/AMDGPUUsage.rst

Removed: 
    


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diff  --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index bfbc77cfe53e..80a7a267e731 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -1719,7 +1719,7 @@ mapping.
    512            VCC_32            32       Vector Condition Code Register
                                              when executing in wavefront 32
                                              mode.
-   513-1023       *Reserved*                 *Reserved for future Vector
+   513-767        *Reserved*                 *Reserved for future Vector
                                              Architectural Registers when
                                              executing in wavefront 32 mode.*
    768            VCC_64            64       Vector Condition Code Register