[PATCH] D108767: [TableGen] Allow target specific flags for RegisterClass

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas added a comment.

In D108767#2967495 <https://reviews.llvm.org/D108767#2967495>, @craig.topper wrote:

> Can you provide an example of why this is a useful thing to have?

For AMDGPU we have different vector registers (VGPRs and AGPRs). There are multiple register classes for them individually and now a superset that combines both A & V registers (AV_32RegClass, for instance).
Currently, the isVGPR() and isAGPR() helper functions that query a specific register class isn't efficient. They are quite slow. 
Having the TSFlags and a single bit for each vector register type will make the query just a quick bitwise operation.


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