[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

[Pengfei Wang via Phabricator via llvm-commits]

pengfei added inline comments.


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Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:3902
+  case X86::VFCMADDCSHZr:
+  case X86::VFCMADDCSHZrb:
+  case X86::VFCMADDCSHZrbk:
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LuoYuanke wrote:
> "b" means rounding. Right?
broadcasting


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Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:3948
+    for (unsigned i = 2; i < Inst.getNumOperands(); i++)
+      if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg())
+        return Warning(Ops[0]->getStartLoc(), "Destination register should be "
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LuoYuanke wrote:
> Sorry, I didn't find the constrain in the spec.
#UD if (dest_reg == src1_reg) or ( dest_reg == src2_reg)


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Comment at: llvm/lib/Target/X86/X86InstrAVX512.td:13640
+                        (v4f32 (OpNode VR128X:$src1, VR128X:$src2)),
+                        0, 0, 0, X86selects, "@earlyclobber $dst">, Sched<[sched.XMM]>;
+    defm rm : AVX512_maskable<opc, MRMSrcMem, f32x_info, (outs VR128X:$dst),
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LuoYuanke wrote:
> I didn't see this flag for other scalar instructions, why we need it for complex instruction?
Because all complex instructions have constrains "dst != src1 && dst != src2". We use earlyclobber to avoid the dst been assigned to src1 or src2.


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  https://reviews.llvm.org/D105269/new/

https://reviews.llvm.org/D105269