[PATCH] D108766: [AArch64] Model Cortex-A55 Q register NEON instructions

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: NickGuy, SjoerdMeijer, fhahn, t.p.northover.
Herald added subscribers: gbedwell, hiraditya, kristof.beyls.
Herald added a reviewer: andreadb.
dmgreen requested review of this revision.
Herald added a project: LLVM.

Cortex-A55 has 2 64bit NEON vector units, meaning a 128bit instruction requires taking both units (and can only be issued as the first instruction in a dual issue pair).  This patch models that by splitting the WriteV SchedWrite into two - the WriteVd that reads/writes only 64bit operands, and the WriteVq that read/writes 128bit registers. The A55 schedule then uses this distinction to model the WriteVq as taking both resource units, and starting a Schedule Group and WriteVd as taking one as before.

I believe this is more correct, even if it does not lead to much better performance.


https://reviews.llvm.org/D108766

Files:
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64SchedA53.td
  llvm/lib/Target/AArch64/AArch64SchedA55.td
  llvm/lib/Target/AArch64/AArch64SchedA57.td
  llvm/lib/Target/AArch64/AArch64SchedA64FX.td
  llvm/lib/Target/AArch64/AArch64SchedCyclone.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
  llvm/lib/Target/AArch64/AArch64SchedFalkor.td
  llvm/lib/Target/AArch64/AArch64SchedKryo.td
  llvm/lib/Target/AArch64/AArch64SchedTSV110.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
  llvm/lib/Target/AArch64/AArch64Schedule.td
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-neon-instructions.s

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