[PATCH] D108727: [X86][MCA] Address other issues with MULX reported in PR51495.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

I believe there is some other llvm-mca bug, because now i can not fix znver3 since llvm-mca simply hangs on existing tests after:

  diff --git a/llvm/lib/Target/X86/X86ScheduleZnver3.td b/llvm/lib/Target/X86/X86ScheduleZnver3.td
  index c2be9ec6085d..be07c069aae1 100644
  --- a/llvm/lib/Target/X86/X86ScheduleZnver3.td
  +++ b/llvm/lib/Target/X86/X86ScheduleZnver3.td
  @@ -617,45 +617,11 @@ defm : Zn3WriteResIntPair<WriteIMul16, [Zn3Multiplier], 3, [3], 3, /*LoadUOps=*/
   defm : Zn3WriteResIntPair<WriteIMul16Imm, [Zn3Multiplier], 4, [4], 2>; // Integer 16-bit multiplication by immediate.
   defm : Zn3WriteResIntPair<WriteIMul16Reg, [Zn3Multiplier], 3, [1], 1>; // Integer 16-bit multiplication by register.
   defm : Zn3WriteResIntPair<WriteIMul32, [Zn3Multiplier], 3, [3], 2>;    // Integer 32-bit multiplication.
  -defm : Zn3WriteResIntPair<WriteMULX32, [Zn3Multiplier], 4, [1], 2>;    // Integer 32-bit Unsigned Multiply Without Affecting Flags.
  -
  -def Zn3MULX32rr : SchedWriteRes<[Zn3Multiplier]> {
  -  let Latency = 4;
  -  let ResourceCycles = [1];
  -  let NumMicroOps = 2;
  -}
  -def : InstRW<[Zn3MULX32rr, WriteIMulH], (instrs MULX32rr)>;
  -
  -def Zn3MULX32rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3Multiplier]> {
  -  let Latency = !add(Znver3Model.LoadLatency, Zn3MULX32rr.Latency);
  -  let ResourceCycles = [1, 1, 2];
  -  let NumMicroOps = Zn3MULX32rr.NumMicroOps;
  -}
  -def : InstRW<[Zn3MULX32rm, WriteIMulHLd,
  -              ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,
  -              ReadAfterLd], (instrs MULX32rm)>;
  -
  +defm : Zn3WriteResIntPair<WriteMULX32, [Zn3Multiplier], 3, [1], 2>;    // Integer 32-bit Unsigned Multiply Without Affecting Flags.
   defm : Zn3WriteResIntPair<WriteIMul32Imm, [Zn3Multiplier], 3, [1], 1>; // Integer 32-bit multiplication by immediate.
   defm : Zn3WriteResIntPair<WriteIMul32Reg, [Zn3Multiplier], 3, [1], 1>; // Integer 32-bit multiplication by register.
   defm : Zn3WriteResIntPair<WriteIMul64, [Zn3Multiplier], 3, [3], 2>;    // Integer 64-bit multiplication.
  -defm : Zn3WriteResIntPair<WriteMULX64, [Zn3Multiplier], 4, [1], 2>;    // Integer 32-bit Unsigned Multiply Without Affecting Flags.
  -
  -def Zn3MULX64rr : SchedWriteRes<[Zn3Multiplier]> {
  -  let Latency = 4;
  -  let ResourceCycles = [1];
  -  let NumMicroOps = 2;
  -}
  -def : InstRW<[Zn3MULX64rr, WriteIMulH], (instrs MULX64rr)>;
  -
  -def Zn3MULX64rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3Multiplier]> {
  -  let Latency = !add(Znver3Model.LoadLatency, Zn3MULX64rr.Latency);
  -  let ResourceCycles = [1, 1, 2];
  -  let NumMicroOps = Zn3MULX64rr.NumMicroOps;
  -}
  -def : InstRW<[Zn3MULX64rm, WriteIMulHLd,
  -              ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,
  -              ReadAfterLd], (instrs MULX64rm)>;
  -
  +defm : Zn3WriteResIntPair<WriteMULX64, [Zn3Multiplier], 3, [1], 2>;    // Integer 32-bit Unsigned Multiply Without Affecting Flags.
   defm : Zn3WriteResIntPair<WriteIMul64Imm, [Zn3Multiplier], 3, [1], 1>; // Integer 64-bit multiplication by immediate.
   defm : Zn3WriteResIntPair<WriteIMul64Reg, [Zn3Multiplier], 3, [1], 1>; // Integer 64-bit multiplication by register.
   defm : Zn3WriteResInt<WriteIMulHLd, [], !add(4, Znver3Model.LoadLatency), [], 0>;  // Integer multiplication, high part.


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