[llvm] 6ffc695 - [AArch64] Remove unpredictable from narrowing instructions.
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 26 01:44:00 PDT 2021
Author: David Green
Date: 2021-08-26T09:43:44+01:00
New Revision: 6ffc6951a370659602faa4b503e1c07a64f02065
URL: https://github.com/llvm/llvm-project/commit/6ffc6951a370659602faa4b503e1c07a64f02065
DIFF: https://github.com/llvm/llvm-project/commit/6ffc6951a370659602faa4b503e1c07a64f02065.diff
LOG: [AArch64] Remove unpredictable from narrowing instructions.
Like other similar instructions the xtn2 family do not have side
effects, and explicitly marking them as such can help improve scheduling
freedom.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/test/CodeGen/AArch64/neon-truncstore.ll
llvm/test/tools/llvm-mca/AArch64/Cortex/A55-neon-instructions.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index ea0c62d2045f3..84d5ba057765d 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -6032,7 +6032,7 @@ multiclass SIMDTwoVectorIntToFP<bit U, bit S, bits<5> opc, string asm,
[(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
}
-
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
class BaseSIMDMixedTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
RegisterOperand inreg, RegisterOperand outreg,
string asm, string outkind, string inkind,
@@ -6055,6 +6055,7 @@ class BaseSIMDMixedTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
let Inst{4-0} = Rd;
}
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
class BaseSIMDMixedTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
RegisterOperand inreg, RegisterOperand outreg,
string asm, string outkind, string inkind,
@@ -6227,6 +6228,7 @@ class BaseSIMDFPCvtTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
let Inst{4-0} = Rd;
}
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
class BaseSIMDFPCvtTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
RegisterOperand outtype, RegisterOperand intype,
string asm, string VdTy, string VnTy,
diff --git a/llvm/test/CodeGen/AArch64/neon-truncstore.ll b/llvm/test/CodeGen/AArch64/neon-truncstore.ll
index 7292841410a05..01ff47997ba91 100644
--- a/llvm/test/CodeGen/AArch64/neon-truncstore.ll
+++ b/llvm/test/CodeGen/AArch64/neon-truncstore.ll
@@ -134,10 +134,10 @@ define void @v8i32_v8i8(<8 x i32> %a, <8 x i8>* %result) {
define void @v16i32_v16i8(<16 x i32> %a, <16 x i8>* %result) {
; CHECK-LABEL: v16i32_v16i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: xtn v2.4h, v2.4s
; CHECK-NEXT: xtn v0.4h, v0.4s
-; CHECK-NEXT: xtn2 v2.8h, v3.4s
+; CHECK-NEXT: xtn v2.4h, v2.4s
; CHECK-NEXT: xtn2 v0.8h, v1.4s
+; CHECK-NEXT: xtn2 v2.8h, v3.4s
; CHECK-NEXT: xtn v0.8b, v0.8h
; CHECK-NEXT: xtn2 v0.16b, v2.8h
; CHECK-NEXT: str q0, [x0]
@@ -150,17 +150,17 @@ define void @v16i32_v16i8(<16 x i32> %a, <16 x i8>* %result) {
define void @v32i32_v32i8(<32 x i32> %a, <32 x i8>* %result) {
; CHECK-LABEL: v32i32_v32i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: xtn v2.4h, v2.4s
; CHECK-NEXT: xtn v0.4h, v0.4s
-; CHECK-NEXT: xtn2 v2.8h, v3.4s
-; CHECK-NEXT: xtn2 v0.8h, v1.4s
-; CHECK-NEXT: xtn v6.4h, v6.4s
; CHECK-NEXT: xtn v4.4h, v4.4s
-; CHECK-NEXT: xtn v0.8b, v0.8h
-; CHECK-NEXT: xtn2 v0.16b, v2.8h
-; CHECK-NEXT: xtn2 v6.8h, v7.4s
+; CHECK-NEXT: xtn v2.4h, v2.4s
+; CHECK-NEXT: xtn v6.4h, v6.4s
+; CHECK-NEXT: xtn2 v0.8h, v1.4s
; CHECK-NEXT: xtn2 v4.8h, v5.4s
+; CHECK-NEXT: xtn2 v2.8h, v3.4s
+; CHECK-NEXT: xtn2 v6.8h, v7.4s
+; CHECK-NEXT: xtn v0.8b, v0.8h
; CHECK-NEXT: xtn v1.8b, v4.8h
+; CHECK-NEXT: xtn2 v0.16b, v2.8h
; CHECK-NEXT: xtn2 v1.16b, v6.8h
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/A55-neon-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/A55-neon-instructions.s
index 501134b143239..c323c7482ca39 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Cortex/A55-neon-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/A55-neon-instructions.s
@@ -1215,8 +1215,8 @@ zip2 v0.8h, v0.8h, v0.8h
# CHECK-NEXT: 1 4 0.50 fcvtmu v0.8h, v0.8h
# CHECK-NEXT: 1 4 0.50 fcvtn v0.2s, v0.2d
# CHECK-NEXT: 1 4 0.50 fcvtn v0.4h, v0.4s
-# CHECK-NEXT: 1 4 0.50 U fcvtn2 v0.4s, v0.2d
-# CHECK-NEXT: 1 4 0.50 U fcvtn2 v0.8h, v0.4s
+# CHECK-NEXT: 1 4 0.50 fcvtn2 v0.4s, v0.2d
+# CHECK-NEXT: 1 4 0.50 fcvtn2 v0.8h, v0.4s
# CHECK-NEXT: 1 4 0.50 fcvtns d21, d14
# CHECK-NEXT: 1 4 0.50 fcvtns s22, s13
# CHECK-NEXT: 1 4 0.50 fcvtns v0.2d, v0.2d
@@ -1247,7 +1247,7 @@ zip2 v0.8h, v0.8h, v0.8h
# CHECK-NEXT: 1 4 0.50 fcvtpu v0.8h, v0.8h
# CHECK-NEXT: 1 4 0.50 fcvtxn s22, d13
# CHECK-NEXT: 1 4 0.50 fcvtxn v0.2s, v0.2d
-# CHECK-NEXT: 1 4 0.50 U fcvtxn2 v0.4s, v0.2d
+# CHECK-NEXT: 1 4 0.50 fcvtxn2 v0.4s, v0.2d
# CHECK-NEXT: 1 4 0.50 fcvtzs d21, d12, #1
# CHECK-NEXT: 1 4 0.50 fcvtzs d21, d14
# CHECK-NEXT: 1 4 0.50 fcvtzs s12, s13
@@ -1742,18 +1742,18 @@ zip2 v0.8h, v0.8h, v0.8h
# CHECK-NEXT: 1 4 0.50 sqxtn v0.2s, v0.2d
# CHECK-NEXT: 1 4 0.50 sqxtn v0.4h, v0.4s
# CHECK-NEXT: 1 4 0.50 sqxtn v0.8b, v0.8h
-# CHECK-NEXT: 1 4 0.50 U sqxtn2 v0.16b, v0.8h
-# CHECK-NEXT: 1 4 0.50 U sqxtn2 v0.4s, v0.2d
-# CHECK-NEXT: 1 4 0.50 U sqxtn2 v0.8h, v0.4s
+# CHECK-NEXT: 1 4 0.50 sqxtn2 v0.16b, v0.8h
+# CHECK-NEXT: 1 4 0.50 sqxtn2 v0.4s, v0.2d
+# CHECK-NEXT: 1 4 0.50 sqxtn2 v0.8h, v0.4s
# CHECK-NEXT: 1 4 0.50 sqxtun b19, h14
# CHECK-NEXT: 1 4 0.50 sqxtun h21, s15
# CHECK-NEXT: 1 4 0.50 sqxtun s20, d12
# CHECK-NEXT: 1 4 0.50 sqxtun v0.2s, v0.2d
# CHECK-NEXT: 1 4 0.50 sqxtun v0.4h, v0.4s
# CHECK-NEXT: 1 4 0.50 sqxtun v0.8b, v0.8h
-# CHECK-NEXT: 1 4 0.50 U sqxtun2 v0.16b, v0.8h
-# CHECK-NEXT: 1 4 0.50 U sqxtun2 v0.4s, v0.2d
-# CHECK-NEXT: 1 4 0.50 U sqxtun2 v0.8h, v0.4s
+# CHECK-NEXT: 1 4 0.50 sqxtun2 v0.16b, v0.8h
+# CHECK-NEXT: 1 4 0.50 sqxtun2 v0.4s, v0.2d
+# CHECK-NEXT: 1 4 0.50 sqxtun2 v0.8h, v0.4s
# CHECK-NEXT: 1 4 0.50 srhadd v0.2s, v0.2s, v0.2s
# CHECK-NEXT: 1 4 0.50 srhadd v0.4h, v0.4h, v0.4h
# CHECK-NEXT: 1 4 0.50 srhadd v0.8b, v0.8b, v0.8b
@@ -2019,9 +2019,9 @@ zip2 v0.8h, v0.8h, v0.8h
# CHECK-NEXT: 1 4 0.50 uqxtn v0.2s, v0.2d
# CHECK-NEXT: 1 4 0.50 uqxtn v0.4h, v0.4s
# CHECK-NEXT: 1 4 0.50 uqxtn v0.8b, v0.8h
-# CHECK-NEXT: 1 4 0.50 U uqxtn2 v0.16b, v0.8h
-# CHECK-NEXT: 1 4 0.50 U uqxtn2 v0.4s, v0.2d
-# CHECK-NEXT: 1 4 0.50 U uqxtn2 v0.8h, v0.4s
+# CHECK-NEXT: 1 4 0.50 uqxtn2 v0.16b, v0.8h
+# CHECK-NEXT: 1 4 0.50 uqxtn2 v0.4s, v0.2d
+# CHECK-NEXT: 1 4 0.50 uqxtn2 v0.8h, v0.4s
# CHECK-NEXT: 1 4 0.50 urecpe v0.2s, v0.2s
# CHECK-NEXT: 1 4 0.50 urecpe v0.4s, v0.4s
# CHECK-NEXT: 1 4 0.50 urhadd v0.16b, v0.16b, v0.16b
@@ -2112,9 +2112,9 @@ zip2 v0.8h, v0.8h, v0.8h
# CHECK-NEXT: 1 4 0.50 xtn v0.2s, v0.2d
# CHECK-NEXT: 1 4 0.50 xtn v0.4h, v0.4s
# CHECK-NEXT: 1 4 0.50 xtn v0.8b, v0.8h
-# CHECK-NEXT: 1 4 0.50 U xtn2 v0.16b, v0.8h
-# CHECK-NEXT: 1 4 0.50 U xtn2 v0.4s, v0.2d
-# CHECK-NEXT: 1 4 0.50 U xtn2 v0.8h, v0.4s
+# CHECK-NEXT: 1 4 0.50 xtn2 v0.16b, v0.8h
+# CHECK-NEXT: 1 4 0.50 xtn2 v0.4s, v0.2d
+# CHECK-NEXT: 1 4 0.50 xtn2 v0.8h, v0.4s
# CHECK-NEXT: 1 4 0.50 zip1 v0.16b, v0.16b, v0.16b
# CHECK-NEXT: 1 4 0.50 zip1 v0.2d, v0.2d, v0.2d
# CHECK-NEXT: 1 4 0.50 zip1 v0.2s, v0.2s, v0.2s
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