[PATCH] D108706: [AArch64][SVE] Optimize ptrue predicate pattern with known sve register width.

[JunMa via Phabricator via llvm-commits]

junparser added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:3836-3839
+  const auto &Subtarget =
+      static_cast<const AArch64Subtarget &>(DAG.getSubtarget());
+  unsigned MinSVESize = Subtarget.getMinSVEVectorSizeInBits();
+  unsigned MaxSVESize = Subtarget.getMaxSVEVectorSizeInBits();
----------------
paulwalker-arm wrote:
> There should already be placeholder for this logic.  If you look at `getPredicateForFixedLengthVector` you'll see a TODO comment.
I uniformly use getPTrue for all of the creation of ptrue in NFC patch, then we can even handle sve.ptrue intrinsic which we have seen in some cases. 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108706/new/

https://reviews.llvm.org/D108706