[PATCH] D108731: [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation

Wed Aug 25 14:40:35 PDT 2021

Carrot created this revision.
Carrot added reviewers: stoklund, craig.topper.
Herald added subscribers: mstorsjo, pengfei, Jim, hiraditya, dylanmckay.
Carrot requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

This patch contains following enhancements to SrcRegMap and DstRegMap:

  1 In findOnlyInterestingUse not only check if the Reg is two address usage, but also check after commutation can it be two address usage.

  2 If a physical register is clobbered, remove SrcRegMap entries that are mapped to it.

  3 In processTiedPairs, when create a new COPY instruction, add a SrcRegMap entry only when the COPY instruction is coalescable. (The COPY src is killed)

With these enhancements isProfitableToCommute can do better commute decision, and finally more register copies are removed.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108731

Files:
  llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
  llvm/test/CodeGen/ARM/fptosi-sat-scalar.ll
  llvm/test/CodeGen/ARM/ssat.ll
  llvm/test/CodeGen/ARM/usat.ll
  llvm/test/CodeGen/AVR/ctpop.ll
  llvm/test/CodeGen/AVR/hardware-mul.ll
  llvm/test/CodeGen/SystemZ/int-cmp-57.ll
  llvm/test/CodeGen/Thumb/pr35836_2.ll
  llvm/test/CodeGen/X86/DynamicCalleeSavedRegisters.ll
  llvm/test/CodeGen/X86/abs.ll
  llvm/test/CodeGen/X86/add-cmov.ll
  llvm/test/CodeGen/X86/addsub-constant-folding.ll
  llvm/test/CodeGen/X86/align-down.ll
  llvm/test/CodeGen/X86/arithmetic_fence2.ll
  llvm/test/CodeGen/X86/avx512-inc-dec.ll
  llvm/test/CodeGen/X86/avx512-mask-op.ll
  llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
  llvm/test/CodeGen/X86/avx512bw-mask-op.ll
  llvm/test/CodeGen/X86/avx512dq-mask-op.ll
  llvm/test/CodeGen/X86/bitreverse.ll
  llvm/test/CodeGen/X86/bswap_tree2.ll
  llvm/test/CodeGen/X86/clear-highbits.ll
  llvm/test/CodeGen/X86/clear-lowbits.ll
  llvm/test/CodeGen/X86/cmp-concat.ll
  llvm/test/CodeGen/X86/combine-mul.ll
  llvm/test/CodeGen/X86/combine-mulo.ll
  llvm/test/CodeGen/X86/combine-or.ll
  llvm/test/CodeGen/X86/combine-sdiv.ll
  llvm/test/CodeGen/X86/combine-smax.ll
  llvm/test/CodeGen/X86/combine-smin.ll
  llvm/test/CodeGen/X86/combine-sra.ll
  llvm/test/CodeGen/X86/combine-srem.ll
  llvm/test/CodeGen/X86/combine-srl.ll
  llvm/test/CodeGen/X86/combine-udiv.ll
  llvm/test/CodeGen/X86/ctpop-combine.ll
  llvm/test/CodeGen/X86/fshl.ll
  llvm/test/CodeGen/X86/fshr.ll
  llvm/test/CodeGen/X86/haddsub-shuf.ll
  llvm/test/CodeGen/X86/haddsub-undef.ll
  llvm/test/CodeGen/X86/haddsub.ll
  llvm/test/CodeGen/X86/hhvm-cc.ll
  llvm/test/CodeGen/X86/horizontal-reduce-fadd.ll
  llvm/test/CodeGen/X86/horizontal-sum.ll
  llvm/test/CodeGen/X86/i128-mul.ll
  llvm/test/CodeGen/X86/iabs.ll
  llvm/test/CodeGen/X86/imul.ll
  llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
  llvm/test/CodeGen/X86/mul-constant-i16.ll
  llvm/test/CodeGen/X86/mul-constant-i32.ll
  llvm/test/CodeGen/X86/mul-constant-i64.ll
  llvm/test/CodeGen/X86/mul-constant-i8.ll
  llvm/test/CodeGen/X86/mul128.ll
  llvm/test/CodeGen/X86/overflow.ll
  llvm/test/CodeGen/X86/palignr.ll
  llvm/test/CodeGen/X86/phaddsub.ll
  llvm/test/CodeGen/X86/pmul.ll
  llvm/test/CodeGen/X86/pmulh.ll
  llvm/test/CodeGen/X86/popcnt.ll
  llvm/test/CodeGen/X86/powi.ll
  llvm/test/CodeGen/X86/pr42998.ll
  llvm/test/CodeGen/X86/recip-fastmath.ll
  llvm/test/CodeGen/X86/rev16.ll
  llvm/test/CodeGen/X86/rot16.ll
  llvm/test/CodeGen/X86/rotate-extract.ll
  llvm/test/CodeGen/X86/rotate-multi.ll
  llvm/test/CodeGen/X86/sat-add.ll
  llvm/test/CodeGen/X86/sdiv_fix.ll
  llvm/test/CodeGen/X86/shift-logic.ll
  llvm/test/CodeGen/X86/smax.ll
  llvm/test/CodeGen/X86/smin.ll
  llvm/test/CodeGen/X86/smul_fix_sat.ll
  llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
  llvm/test/CodeGen/X86/sqrt-fastmath.ll
  llvm/test/CodeGen/X86/sse-minmax.ll
  llvm/test/CodeGen/X86/sshl_sat.ll
  llvm/test/CodeGen/X86/ssub_sat.ll
  llvm/test/CodeGen/X86/ssub_sat_vec.ll
  llvm/test/CodeGen/X86/stack-folding-fp-avx512.ll
  llvm/test/CodeGen/X86/stack-folding-int-avx512.ll
  llvm/test/CodeGen/X86/tbm-intrinsics-fast-isel-x86_64.ll
  llvm/test/CodeGen/X86/tbm-intrinsics-fast-isel.ll
  llvm/test/CodeGen/X86/udiv_fix_sat.ll
  llvm/test/CodeGen/X86/umax.ll
  llvm/test/CodeGen/X86/umin.ll
  llvm/test/CodeGen/X86/umul_fix.ll
  llvm/test/CodeGen/X86/umul_fix_sat.ll
  llvm/test/CodeGen/X86/umulo-128-legalisation-lowering.ll
  llvm/test/CodeGen/X86/umulo-64-legalisation-lowering.ll
  llvm/test/CodeGen/X86/unfold-masked-merge-scalar-variablemask.ll
  llvm/test/CodeGen/X86/urem-lkk.ll
  llvm/test/CodeGen/X86/urem-seteq-vec-nonzero.ll
  llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll
  llvm/test/CodeGen/X86/vec_ctbits.ll
  llvm/test/CodeGen/X86/vec_minmax_sint.ll
  llvm/test/CodeGen/X86/vec_minmax_uint.ll
  llvm/test/CodeGen/X86/vec_saddo.ll
  llvm/test/CodeGen/X86/vec_sdiv_to_shift.ll
  llvm/test/CodeGen/X86/vec_shift6.ll
  llvm/test/CodeGen/X86/vec_smulo.ll
  llvm/test/CodeGen/X86/vec_ssubo.ll
  llvm/test/CodeGen/X86/vec_umulo.ll
  llvm/test/CodeGen/X86/vector-bitreverse.ll
  llvm/test/CodeGen/X86/vector-ext-logic.ll
  llvm/test/CodeGen/X86/vector-fshl-128.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-sub128.ll
  llvm/test/CodeGen/X86/vector-fshr-128.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-sub128.ll
  llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
  llvm/test/CodeGen/X86/vector-lzcnt-128.ll
  llvm/test/CodeGen/X86/vector-mul.ll
  llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
  llvm/test/CodeGen/X86/vector-popcnt-128.ll
  llvm/test/CodeGen/X86/vector-reduce-fadd-fast.ll
  llvm/test/CodeGen/X86/vector-reduce-fadd.ll
  llvm/test/CodeGen/X86/vector-reduce-fmax.ll
  llvm/test/CodeGen/X86/vector-reduce-fmul-fast.ll
  llvm/test/CodeGen/X86/vector-reduce-fmul.ll
  llvm/test/CodeGen/X86/vector-reduce-smax.ll
  llvm/test/CodeGen/X86/vector-reduce-umax.ll
  llvm/test/CodeGen/X86/vector-rotate-128.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
  llvm/test/CodeGen/X86/vector-shuffle-combining.ll
  llvm/test/CodeGen/X86/vector-trunc-math.ll
  llvm/test/CodeGen/X86/vector-tzcnt-128.ll
  llvm/test/CodeGen/X86/vector-unsigned-cmp.ll
  llvm/test/CodeGen/X86/vselect-minmax.ll
  llvm/test/CodeGen/X86/vselect-zero.ll
  llvm/test/CodeGen/X86/x86-no_caller_saved_registers-preserve.ll
  llvm/test/CodeGen/X86/x86-shifts.ll

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