[PATCH] D108727: [X86][MCA] Address other issues with MULX reported in PR51495.

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb created this revision.
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It turns out that SchedWrite `WriteIMulH` was always assigned to the low half of the result of a MULX (rather than to the high half).

To avoid confusion, this patch swaps the two MULX writes in the tablegen definition of MULX32/64.
That way, writes names better describe what they refere to; this also avoids further complications, if in future we decide to reuse some of these writes to also model the second register write performed by some scalar integer multiply instructions.
I also had to swap the latency values for the two writes to make sure that the change is effectively an NFC. In fact, none of the existing x86 tests were affected by this small refactoring.

This patch also fixes a bug in MCA: a wrong latency value was propagated for instructions that perform multiple writes to a same register.
This last issue was found by Roman while testing MULX on targets that define a different latency for the Low/High part of the result.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108727

Files:
  llvm/lib/MCA/HardwareUnits/RegisterFile.cpp
  llvm/lib/Target/X86/X86InstrArithmetic.td
  llvm/lib/Target/X86/X86SchedBroadwell.td
  llvm/lib/Target/X86/X86SchedHaswell.td
  llvm/lib/Target/X86/X86SchedSandyBridge.td
  llvm/lib/Target/X86/X86SchedSkylakeClient.td
  llvm/lib/Target/X86/X86SchedSkylakeServer.td
  llvm/test/tools/llvm-mca/X86/Haswell/mulx-same-regs.s
  llvm/test/tools/llvm-mca/X86/SkylakeClient/mulx-same-regs.s

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