[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0-rc1 spec

[Yueh-Ting Chen via Phabricator via llvm-commits]

eopXD created this revision.
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Let llvm arch string able to catch the zvl sub-extension. Also assert that
`RVVVectorBitsMin` is at least the length specified zvl (if specified).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108694

Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h

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