[PATCH] D108669: [WebAssembly] Fix up out-of-range BUILD_VECTOR lane constants

[Thomas Lively via Phabricator via llvm-commits]

tlively created this revision.
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Fixes PR51605 in which a DAG combine and legalization sequence generated
out-of-range constants in BUILD_VECTOR lanes. In the v16i8 case, the constants
were 255, which would be in range if DAG ISel used unsigned constants, but it is
out of range because DAG ISel uses signed constants.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108669

Files:
  llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
  llvm/test/CodeGen/WebAssembly/simd-pr51605.ll


Index: llvm/test/CodeGen/WebAssembly/simd-pr51605.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/WebAssembly/simd-pr51605.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -verify-machineinstrs -mattr=+simd128 | FileCheck %s
+
+; Regression test for an issue in which DAG combines created a constant i8x16
+; vector with lane values of 255, which was outside the -128 to 127 range
+; expected by our ISel patterns (and similar for the i16 version) and caused an
+; ISel failure. The fix was to adjust out-of-range values manually in
+; BUILD_VECTOR lowering.
+
+target triple = "wasm32-unknown-unknown"
+
+define <4 x i8> @test_i8(<4 x i8> %b) {
+  %c = and <4 x i8> %b, <i8 1, i8 1, i8 1, i8 1>
+  %d = xor <4 x i8> %c, <i8 1, i8 1, i8 1, i8 1>
+  ret <4 x i8> %d
+}
+
+define <4 x i16> @test_i16(<4 x i16> %b) {
+  %c = and <4 x i16> %b, <i16 1, i16 1, i16 1, i16 1>
+  %d = xor <4 x i16> %c, <i16 1, i16 1, i16 1, i16 1>
+  ret <4 x i16> %d
+}
Index: llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
===================================================================
--- llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -2046,7 +2046,18 @@
     SmallVector<SDValue, 16> ConstLanes;
     for (const SDValue &Lane : Op->op_values()) {
       if (IsConstant(Lane)) {
-        ConstLanes.push_back(Lane);
+        // Values may need to be fixed so that they will sign extend to be
+        // within the expected range during ISel.
+        auto *Const = dyn_cast<ConstantSDNode>(Lane.getNode());
+        int64_t Val = Const ? Const->getSExtValue() : 0;
+        uint64_t LaneBits = 128 / Lanes;
+        if (Const &&
+            (Val < -(1 << (LaneBits - 1)) || Val > (1 << (LaneBits - 1)) - 1)) {
+          auto NewVal = ((uint64_t)Val % (1u << LaneBits)) - (1u << LaneBits);
+          ConstLanes.push_back(DAG.getConstant(NewVal, SDLoc(Lane), MVT::i32));
+        } else {
+          ConstLanes.push_back(Lane);
+        }
       } else if (LaneT.isFloatingPoint()) {
         ConstLanes.push_back(DAG.getConstantFP(0, DL, LaneT));
       } else {


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