[PATCH] D108663: [RISCV] Insert a sext_inreg when type legalizing i32 shl by constant on RV64.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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Similar to what we do for add/sub/mul.

This can help remove some sext.w. There are some regressions on
some bswap tests, but I have an idea how to fix that for a follow up.

A new PACKW pattern is added to handle the new sext_inreg placement.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108663

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/alu32.ll
  llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
  llvm/test/CodeGen/RISCV/copysign-casts.ll
  llvm/test/CodeGen/RISCV/mul.ll
  llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
  llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
  llvm/test/CodeGen/RISCV/rv64zbb.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll

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