[PATCH] D108633: [AArch64] Generate smov in place of sext(fmov(...))

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:2496-2499
+  def : Pat<(sext_inreg (vector_extract (nxv16i8 ZPR:$vec), VectorIndexH:$index), i8),
+            (i32 (SMOVvi8to32 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index))>;
+  def : Pat<(sext_inreg (anyext (vector_extract (nxv16i8 ZPR:$vec), VectorIndexH:$index)), i8),
+            (i64 (SMOVvi8to64 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index))>;
----------------
These should be using VectorIndexB.


================
Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:2501-2504
+  def : Pat<(sext_inreg (vector_extract (nxv8i16 ZPR:$vec), VectorIndexH:$index), i16),
+            (i32 (SMOVvi16to32 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index))>;
+  def : Pat<(sext_inreg (anyext (vector_extract (nxv8i16 ZPR:$vec), VectorIndexH:$index)), i16),
+            (i64 (SMOVvi16to64 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index))>;
----------------
These should only use VectorIndexH.


================
Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:2506-2507
+
+  def : Pat<(sext (vector_extract (nxv4i32 ZPR:$vec), VectorIndexH:$index)),
+            (i64 (SMOVvi32to64 (v4i32 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index))>;
 } // End HasSVEorStreamingSVE
----------------
This should be using VectorIndexS.


================
Comment at: llvm/test/CodeGen/AArch64/aarch64-smov-gen.ll:5-17
+define dso_local i32 @_Z7foo8_32u10__SVInt8_t(<vscale x 16 x i8> %a) local_unnamed_addr #0 {
+; CHECK-LABEL: _Z7foo8_32u10__SVInt8_t:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ptrue p0.b
+; CHECK-NEXT:    sminv b0, p0, z0.b
+; CHECK-NEXT:    smov w0, v0.b[0]
+; CHECK-NEXT:    ret
----------------
Please simplify the tests. For example
```
target triple = "aarch64-unknown-linux-gnu"

define i32 @extract_s8(<vscale x 16 x i8> %a) #0 {
  %elt = extractelement <vscale x 16 x i8> %a, i32 15
  %conv = sext i8 %elt to i32
  ret i32 %conv
}

attributes #0 = { "target-features"="+sve" }
```

Should be enough to test the new patterns.

Given the VectorIndex# issues above I think it's worth having tests for out-of-range indices as well. I guess testing `extract element VF-1` and `extract element VF` will cover the good and less good cases.



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108633/new/

https://reviews.llvm.org/D108633